Semiconductor device and manufacturing method
A semiconductor device includes; cell transistors on a substrate, lower electrodes respectively connected to the cell transistors, arranged according to a first pitch in a first horizontal direction, and extending in a vertical direction, and an etching stop layer surrounding lower sidewalls of the lower electrodes and arranged at a level higher than a level of the cell transistors, wherein the etching stop layer includes a first portion vertically overlapping the lower electrodes and a second portion laterally surrounding the first portion, and the second portion includes recesses arranged according to a second pitch in the first horizontal direction.
1. A semiconductor device comprising:
a substrate including a cell area and a peripheral circuit area, wherein the cell area includes cell transistors and the peripheral circuit area includes a peripheral circuit;
an etching stop layer including a first portion of the etching stop layer arranged in the cell area and a second portion of the etching stop layer arranged in the peripheral circuit area; and
a capacitor structure arranged in the cell area and including lower electrodes respectively connected to the cell transistors via the first portion of the etching stop layer and arranged according to a first pitch,
wherein the second portion of the etching stop layer includes recesses arranged according to a second pitch substantially the same as the first pitch,
wherein the etching stop layer comprises a first thickness at each recess and a second thickness between adjacent recesses, and
wherein the second thickness is greater than the first thickness.
2. The semiconductor device of claim 1 , wherein the recesses are arranged in a hexagonal pattern,
the lower electrodes are arranged in a hexagonal pattern,
the first pitch is a distance in a first horizontal direction between centers of two adjacent lower electrodes, and
the second pitch is a distance in the first horizontal direction between centers of two adjacent recesses.
3. The semiconductor device of claim 1 ,
wherein a bottom portion of each of the lower electrodes has a first width, and
wherein each of the recesses has a second width that ranges from between about 100% to about 150% of the first width.
4. The semiconductor device of claim 1 , wherein the recesses are defined in an upper surface of the second portion of the etching stop layer, and a lower surface of the second portion of the etching stop layer is flat.
5. The semiconductor device of claim 1 , further comprising:
an interlayer insulating layer on the second portion of the etching stop layer; and
a peripheral circuit contact penetrating the interlayer insulating layer and the second portion of the etching stop layer to electrically connect to the peripheral circuit.
6. The semiconductor device of claim 5 , wherein a lower surface of the interlayer insulating layer includes protrusions conforming to the recesses.
7. The semiconductor device of claim 1 , wherein the recesses are arranged in a matrix, and the lower electrodes are arranged in a matrix.
8. The semiconductor device of claim 1 , further comprising:
a buffer insulating layer on the second portion of the etching stop layer; and
an interlayer insulating layer on the buffer insulating layer,
wherein the buffer insulating layer includes openings respectively corresponding to the recesses.
9. The semiconductor device of claim 8 , wherein inner walls of the recesses and inner walls of the openings are respectively and continuously connected.
10. The semiconductor device of claim 8 , wherein the openings are arranged in a hexagonal pattern.
11. The semiconductor device of claim 1 , wherein the capacitor structure further includes:
a capacitor dielectric layer covering upper surfaces of the lower electrodes and extending onto the first portion of the etching stop layer; and
an upper electrode covering the lower electrodes on the capacitor dielectric layer.
12. A semiconductor device comprising:
cell transistors on a substrate;
lower electrodes respectively connected to the cell transistors, arranged according to a first pitch in a first horizontal direction, and extending in a vertical direction; and
an etching stop layer surrounding lower sidewalls of the lower electrodes and arranged at a level higher than a level of the cell transistors, wherein the etching stop layer includes a first portion vertically overlapping the lower electrodes and a second portion laterally surrounding the first portion, and the second portion includes recesses arranged according to a second pitch in the first horizontal direction,
wherein the etching stop layer comprises a first thickness at each recess and a second thickness between adjacent recesses, and
wherein the second thickness is greater than the first thickness.
13. The semiconductor device of claim 12 , wherein the recesses are arranged in a hexagonal pattern, and the lower electrodes are arranged in a hexagonal pattern.
14. The semiconductor device of claim 12 , further comprising:
an interlayer insulating layer on the second portion of the etching stop layer; and
a peripheral circuit contact penetrating the interlayer insulating layer and the second portion of the etching stop layer.
15. The semiconductor device of claim 14 , wherein a lower surface of the second portion of the etching stop layer is flat, and
a lower surface of the interlayer insulating layer includes protrusions conforming to the recesses.
16. The semiconductor device of claim 12 , further comprising:
a buffer insulating layer on the second portion of the etching stop layer; and
an interlayer insulating layer on the buffer insulating layer,
wherein the buffer insulating layer includes openings at locations respectively corresponding to the recesses.
17. The semiconductor device of claim 12 ,
wherein bottom portions of each of the lower electrodes has a first width, and
wherein each of the recesses has a second width that ranges from between about 100% to about 150% of the first width.
18. A semiconductor device comprising:
a substrate including a cell area and a peripheral circuit area, wherein the cell area includes cell transistors and the peripheral circuit area includes a peripheral circuit;
an etching stop layer including a first portion of the etching stop layer in the cell area and a second portion of the etching stop layer in the peripheral circuit area;
a capacitor structure in the cell area, wherein the capacitor structure includes lower electrodes, a capacitor dielectric layer covering upper surfaces of the lower electrodes, and an upper electrode on the capacitor dielectric layer and covering the lower electrodes, wherein the lower electrodes are respectively connected to the cell transistors via the first portion of the etching stop layer and are arranged according to a first pitch in a first horizontal direction;
an interlayer insulating layer on the second portion of the etching stop layer; and
a peripheral circuit contact penetrating the interlayer insulating layer and the second portion of the etching stop layer to electrically connect to the peripheral circuit,
wherein the second portion of the etching stop layer includes recesses arranged according to a second pitch in the first horizontal direction,
wherein the etching stop layer comprises a first thickness at each recess and a second thickness between adjacent recesses, and
wherein the second thickness is greater than the first thickness.
19. The semiconductor device of claim 1 , wherein the first thickness and the second thickness extend in a vertical direction from an upper surface of the substrate.
20. The semiconductor device of claim 12 , wherein the first thickness and the second thickness extend in a vertical direction from an upper surface of the substrate.