IP Library Granted Patent US 9,754,826
Granted Patent B2
US 9,754,826 · App. 15/155,478 · Granted Sep 5, 2017

Semiconductor devices and methods of manufacturing the same

Inventors: Jong-Won Hong (Hwaseong-si, KR); Hei-Seung Kim (Suwon-si, KR); Kyoung-Hee Nam (Seoul, KR); In-Sun Park (Seoul, KR); Jong-Myeong Lee (Seongnam-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L21/76879H01L21/2885H01L21/76846H01L21/76847H01L21/76861H01L21/76864H01L21/76873H01L21/76877H01L21/76882H01L23/53238H01L27/10897H01L27/11529H01L27/10894H01L2221/1089H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,754,826
App. No.
15/155,478
Granted
Sep 5, 2017
Kind
B2
Abstract

A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

Claims (19)

1. A method of manufacturing a semiconductor device, comprising:

forming a trench on an insulating interlayer on a substrate;

forming a first seed layer on an inner wall of the trench and on the insulating interlayer, the first seed layer having a first thickness on an upper portion of the trench greater than a second thickness on a lower portion of the trench;

forming a preliminary metal layer filling the lower portion of the trench by performing a reflow process on the first seed layer;

forming a wetting improvement layer on a portion of the preliminary metal layer on the upper portion of the trench; and

forming a metal layer filling the trench by an electrolytic plating process.

2. The method of claim 1 , wherein the forming a metal layer includes performing the electrolytic plating process using an additive and an electrolyte, the additive having a suppressor, an accelerator and a leveler, and the electrolyte including a copper ion, and

wherein the forming a wetting improvement layer includes forming at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

3. The method of claim 1 , further comprising:

forming a barrier layer on the inner wall of the trench and on the insulating interlayer prior to the forming a first seed layer.

4. The method of claim 1 , wherein the forming a first seed layer includes performing a sputtering process using copper as a target when a bias power is applied to the substrate.

5. The method of claim 1 , wherein the forming a preliminary metal layer exposes a portion of the inner wall of the trench, the method further comprising:

forming a second seed layer on the exposed portion of the inner wall of the trench.

6. The method of claim 4 , wherein the forming a wetting improvement layer forms the wetting improvement layer on the preliminary metal layer in the trench.

7. The method of claim 1 , further comprising:

reducing oxidized portions of the preliminary metal layer and the wetting improvement layer prior to the forming a metal layer.

8. The method of claim 1 , further comprising:

planarizing the metal layer until the insulating interlayer is exposed after the forming a metal layer,

wherein the wetting improvement layer on the upper portion of the trench is removed by the planarization of the metal layer.

Priority Claims (1)
KR 10-2011-0126479 · Nov 30, 2011 · national
Continuity (2)
Division 13588393 · Aug 17, 2012
Related Publication 20160260635A1 · Sep 8, 2016