Methods and apparatus to facilitate atomic operations in victim cache
Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.
1. A device comprising:
a cache memory configured to store data;
a cache controller; and
a cache store queue coupled between the cache controller and the cache memory, wherein:
the cache store queue includes an arithmetic unit; and
the cache controller is configured to:
receive a histogram operation directed to the data;
cause the arithmetic unit to:
receive the data from the cache memory; and
generate a histogram based on the data; and
cause the histogram to be stored in the cache memory.
2. The device of claim 1 , wherein:
the cache memory is a victim cache memory;
the cache store queue is a victim cache store queue; and
the device further includes a main cache memory coupled to the cache controller.
3. The device of claim 1 , wherein the cache controller is further configured to:
receive a weight associated with the histogram; and
cause the arithmetic unit to generate the histogram based on the weight.
4. The device of claim 1 , wherein the cache controller is further configured to:
receive a bin size associated with the histogram; and
cause the arithmetic unit to generate the histogram based on the bin size.
5. The device of claim 1 , wherein the cache controller is further configured to:
receive an indication of whether a bin value of the histogram is signed or unsigned; and
cause the arithmetic unit to generate the histogram based on the indication.
6. The device of claim 1 , wherein the cache controller is further configured to:
receive an indication of whether a bin of the histogram is to roll over when a maximum value is reached; and
cause the arithmetic unit to generate the histogram based on the indication.
7. The device of claim 1 further comprising error correcting code (ECC) logic coupled to the arithmetic unit.
8. The device of claim 1 further comprising an arbitration manager circuit coupled between the arithmetic unit and the cache memory and configured to arbitrate storage of the histogram.
9. The device of claim 1 further including a modified, exclusive, shared, invalid (MESI) circuit configured to determine a state of a memory address associated with the histogram operation.
10. The device of claim 9 , wherein the MESI circuit is configured to, based on the memory address being associated with a shared state:
provide an exclusive state request for the memory address; and
cause the histogram to be stored in the cache memory based on the exclusive state request being granted.
11. The device of claim 1 further comprising a processor coupled to the cache controller and configured to provide the histogram operation.
12. The device of claim 11 , wherein:
the cache memory is a level-one (L1) cache memory; and
the cache controller is an L1 cache controller.
13. A method comprising:
receiving, from a processor by a cache system, a histogram operation directed to data stored in a cache memory of the cache system;
receiving the data from the cache memory;
generating a histogram based on the data by a cache store queue coupled to the cache memory; and
storing the histogram in the cache memory.
14. The method of claim 13 , wherein:
the cache memory is a victim cache memory;
the cache store queue is a victim cache store queue; and
the cache system further includes a main cache memory.
15. The method of claim 13 , wherein:
the histogram operation is associated with a weight; and
the histogram is a weighted histogram based on the weight.
16. The method of claim 13 , wherein the histogram operation specifies at least one of: a bin size, an indication of whether a bin value is signed or unsigned, or an indication of whether a bin rolls over when a maximum value is reached.
17. The method of claim 13 further comprising:
generating error correcting code (ECC) data for the histogram; and
storing the ECC data in the cache memory.
18. The method of claim 13 further comprising determining a modified, exclusive, shared, invalid (MESI) state of a memory address associated with the histogram operation.
19. The method of claim 18 further comprising, based on the memory address being associated with a shared state:
providing an exclusive state request for the memory address; and
causing the histogram to be stored in the cache memory based on the exclusive state request being granted.
20. The method of claim 13 , wherein:
the cache system is a level-one (L1) cache system; and
the cache memory is an L1 cache memory.