Delayed cache entry invalidation update for potential overwrite re-use
Techniques are disclosed relating to cache control in cache hierarchies. In some embodiments, processor execution circuitry is configured to perform operations on input operand data from a first-level cache, including a first operation that reads first data from an entry in the first-level cache and signals an invalidation of the first data. Control circuitry may set an indicator, in response to the first operation, to indicate that the entry in the first-level cache has a pending invalidation (e.g., a last-use indicator). The control circuitry may, in response to a second operation overwriting the entry in the first-level cache while the indicator is set, clear the indicator without invalidating a corresponding entry in a second-level cache. This may advantageously reduce invalidate operations and bandwidth to the second-level cache.
1 . An apparatus, comprising:
first-level cache circuitry;
second-level cache circuitry, wherein the first-level cache circuitry and second-level cache circuitry are at different levels in a cache hierarchy;
processor execution circuitry configured to perform operations on input operand data from the first-level cache circuitry, including a first operation that reads first data from an entry in the first-level cache circuitry and signals an invalidation of the first data; and
control circuitry configured to:
set an indicator, in response to the first operation, to indicate that the entry in the first-level cache circuitry has a pending invalidation;
in response to a second operation overwriting the entry in the first-level cache circuitry while the indicator is set, clear the indicator without invalidating a corresponding entry in the second-level cache circuitry; and
in response to eviction of the entry in the first-level cache circuitry based on a replacement policy while the indicator is set, invalidate the corresponding entry in the second-level cache circuitry.
2 . The apparatus of claim 1 , wherein:
the first-level cache circuitry is an operand cache;
the second-level cache circuitry is a register file or a register data cache; and
the first operation is a register read with a last-use indication that signals the invalidation.
3 . The apparatus of claim 2 , wherein the operand cache includes entries configured to store register data for multiple threads of single-instruction multiple-thread (SIMT) groups of graphics programs executed by the processor execution circuitry.
4 . The apparatus of claim 1 , wherein the control circuitry is configured to guarantee suppression of an invalidate operation to the second-level cache circuitry for the first operation if an immediately-subsequent operation to the first operation overwrites the entry in the first-level cache circuitry.
5 . The apparatus of claim 4 , wherein the processor execution circuitry executes a program that was compiled to re-use operand locations for instructions subsequent to operations that signal an invalidation of their read data.
6 . The apparatus of claim 1 , wherein the first-level cache circuitry is a closest cache level to the processor execution circuitry in the cache hierarchy.
7 . The apparatus of claim 1 , wherein the first operation is a load operation that specifies a memory address.
8 . The apparatus of claim 1 , wherein the entry in the first-level cache circuitry includes a valid indication.
9 . The apparatus of claim 1 , further comprising:
replacement control circuitry configured to prioritize entries in the first-level cache circuitry indicated as having a pending invalidation for eviction.
10 . The apparatus of claim 1 , wherein the second-level cache circuitry is a write-back cache and is inclusive of data from locations cached in the first-level cache circuitry.
11 . The apparatus of claim 1 , further comprising:
eviction port circuitry configured to handle evictions only for entries in the first-level cache circuitry indicated as having a pending invalidation.
12 . A method, comprising:
performing, by a computing system, operations on input operand data from a first-level cache, including a first operation that reads first data from an entry in the first-level cache and signals an invalidation of the first data;
setting, by the computing system, an indicator, in response to the first operation, to indicate that the entry in the first-level cache has a pending invalidation; and
clearing, by the computing system in response to a second operation overwriting the entry in the first-level cache while the indicator is set, the indicator without invalidating a corresponding entry in a second-level cache, wherein the second-level cache is a write-back cache and is inclusive of data from locations cached in the first-level cache.
13 . The method of claim 12 , wherein:
the first-level cache is an operand cache;
the second-level cache is a register file or a register data cache; and
the first operation is a register read with a last-use indication that signals the invalidation.
14 . The method of claim 12 , wherein:
the computing system guarantees suppression of an invalidate operation to the second-level cache for the first operation if an immediately-subsequent operation to the first operation overwrites the entry in the first-level cache.
15 . The method of claim 14 , further comprising:
compiling a program that includes the first operation, including selecting a destination for the immediately-subsequent operation to overwrite the entry in the first-level cache.
16 . The method of claim 12 , wherein the first operation is a load operation that specifies a memory address.
17 . The method of claim 12 , further comprising:
prioritizing, by the computing system, entries in the first-level cache indicated as having a pending invalidation for eviction.
18 . The method of claim 12 , wherein the second-level cache is a write-back cache and is inclusive of data from locations cached in the first-level cache.
19 . A non-transitory computer-readable medium having instructions stored thereon that are executable by a computing device to perform operations comprising:
compiling a program for execution by a processor that includes a first-level cache and a second-level cache, including:
generating a first operation that reads first data and signals an invalidation of the first data; and
generating a second operation, subsequent to the first operation in program order, including selecting a destination for the second operation to overwrite the first data;
wherein the processor includes control circuitry configured to:
read the first data from an entry in the first-level cache for the first operation;
set an indicator, in response to the first operation, to indicate that the entry in the first-level cache has a pending invalidation; and
in response to the second operation overwriting the entry in the first-level cache while the indicator is set, clear the indicator without invalidating a corresponding entry in the second-level cache.