MRAM stacks and memory devices

1. A memory stack, comprising:

a spin-orbit torque layer;

a magnetic bias layer disposed below the spin-orbit torque layer and having a first magnetic anisotropy; and

a free layer disposed above the spin-orbit torque layer and having a second magnetic anisotropy perpendicular to the first magnetic anisotropy,

wherein a width of the magnetic bias layer is different from a width of the free layer.

2. The memory stack of claim 1 , wherein the spin-orbit torque layer comprises W, Pt, AuPt or a combination thereof.

3. The memory stack of claim 1 , wherein a width of the magnetic bias layer is greater than a width of the free layer.

4. The memory stack of claim 1 , wherein the free layer comprises FeCo, CoFeB, FeB or a combination thereof.

5. The memory stack of claim 1 , wherein the magnetic bias layer comprises Co, CoNi or a combination thereof.

6. The memory stack of claim 1 , further comprising a buffer layer disposed below the magnetic bias, wherein the buffer layer comprises Ta, Ru, TiN, TaN, W or a combination thereof.

7. The memory stack of claim 1 , further comprising a magnetic fixed layer disposed over the free layer.

8. A memory stack, comprising:

a spin-orbit torque layer; and

a synthetic free layer disposed over the spin-orbit torque layer and comprising:

a first free layer with a first magnetic anisotropy perpendicular to a upper surface of the spin-orbit torque layer; and

a second free layer with a second magnetic anisotropy parallel to the upper surface of the spin-orbit torque layer,

wherein the first free layer is in direct contact with the spin-orbit torque layer.

9. The memory stack of claim 8 , wherein the first free layer comprises Co, CoNi or a combination thereof.

10. The memory stack of claim 8 , wherein the synthetic free layer further comprises a non-magnetic metal spacer between the first free layer and the second free layer.

11. The memory stack of claim 8 , wherein the second free layer comprises Fe, Co, Ni, FeCo, CoNi, CoFeB, FeB, FePt, FePd or a combination thereof.

12. The memory stack of claim 8 , further comprising a tunneling barrier layer disposed over the synthetic free layer.

13. The memory stack of claim 12 , further comprising a reference layer disposed over the tunneling barrier layer.

14. The memory stack of claim 13 , wherein the reference layer comprises Fe, Co, Ni, FeCo, CoNi, CoFeB, FeB, FePt, FePd or a combination thereof.

15. The memory stack of claim 13 , further comprising a capping structure disposed over the reference layer, wherein the capping structure comprises Ta, Ru or a combination thereof.

16. A memory device, comprising:

a substrate;

a first transistor disposed over the substrate and having a first source/drain region; and

a MRAM cell disposed over the substrate and comprising:

a first bottom electrode electrically coupled to the first source/drain region;

a spin-orbit torque layer disposed over the first and second bottom electrodes;

a synthetic free layer disposed over the spin-orbit torque layer and comprising two layers configured to have magnetic anisotropies perpendicular to each other; and

a top electrode disposed over the synthetic free layer and electrically coupled to a bit line.

17. The memory device of claim 16 , wherein the layer of the synthetic free layer that is in physical contact with the spin-orbit torque layer forms a perpendicular magnetic anisotropy with the spin-orbit torque layer.

18. The memory device of claim 16 , further comprising:

a second transistor disposed over the substrate and having a second source/drain region; and

a second bottom electrode disposed laterally aside the first bottom electrode and electrically coupled to the first source/drain region.

19. The memory device of claim 16 , further comprising:

a tunneling barrier layer disposed over the synthetic free layer; and

a reference layer disposed over the tunneling barrier layer,

wherein the top electrode is disposed over the reference layer.