SRAM structures
Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.
1. A memory device, comprising:
a memory array comprising:
a first subarray including a plurality of first SRAM cells,
a second subarray including a plurality of second SRAM cells, and
a word line spanning over the first subarray and the second subarray and electrically coupled to at least one of the plurality of first SRAM cells and at least one of the plurality of second SRAM cells; and
a word line driver adjacent the second subarray and away from the first subarray
wherein a threshold voltage of each n-type transistor in the plurality of first SRAM cells is smaller than a threshold voltage of each n-type transistor in the plurality second SRAM cells.
2. The memory device of claim 1 ,
wherein the memory array has a first length along a direction,
wherein the first subarray has a second length along the direction,
wherein the first length is smaller than the first length.
3. The memory device of claim 1 ,
wherein each n-type transistor in the plurality of first SRAM cells includes a first work function stack,
wherein each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.
4. The memory device of claim 3 ,
wherein each p-type transistor in the plurality of first SRAM cells includes the second work function stack,
wherein each p-type transistor in the plurality of second SRAM cells includes the first work function stack.
5. The memory device of claim 4 , wherein a threshold voltage of each p-type transistor in the plurality of first SRAM cells is greater than a threshold voltage of each p-type transistor in the plurality of second SRAM cells.
6. The memory device of claim 4 ,
wherein the first work function stack includes a titanium aluminum layer
wherein the second work function stack includes at least one titanium nitride layer and the titanium aluminum layer disposed over the at least one titanium nitride layer.
7. The memory device of claim 1 , wherein each of the plurality of first SRAM cells and the plurality of second SRAM cells includes:
two p-type transistors disposed over an n-type well;
two n-type transistors disposed over a first p-type well; and
two n-type transistors disposed over a second p-type well,
wherein the n-type well is disposed directly between the first p-type well and the second p-type well.
8. The memory device of claim 1 ,
wherein the memory array and the first subarray are both rectangular in shape,
wherein the first subarray is disposed at a corner of the memory array,
wherein the second subarray surrounds the first subarray.
9. The memory device of claim 1 ,
wherein the word line driver comprises a high-speed region and a low-leakage region,
wherein a threshold voltage of each n-type transistor in the high-speed region is smaller than a threshold voltage of each n-type transistor in the low-leakage region.
10. The memory device of claim 9 , wherein the second subarray is addressed by the high-speed region.
11. A memory device, comprising:
a Static Random Access Memory (SRAM) array having a length extending along a first direction and a height extending along a second direction perpendicular to the first direction, the SRAM array comprising:
a first subarray including a plurality of first SRAM cells, and
a second subarray including a plurality of second SRAM cells;
a word line driver disposed adjacent to the SRAM array along the first direction and coupled to the plurality of first SRAM cells and the plurality of second SRAM cells via a plurality of word lines extending along the first direction; and
a read/write block adjacent to the SRAM array along the second direction,
wherein the first subarray is spaced apart from the word line driver by at least a portion of the second subarray,
wherein at least one word line of the plurality of word lines is electrically coupled to at least one of the plurality of first SRAM cells and at least one of the plurality of second SRAM cells
wherein a threshold voltage of each n-type transistor in the plurality of first SRAM cells is smaller than a threshold voltage of each n-type transistor in the plurality second SRAM cells.
12. The memory device of claim 11 , wherein each of the plurality of first SRAM cells and the plurality of second SRAM cells is electrically coupled to the read/write block by a plurality of bit lines extending along the second direction.
13. The memory device of claim 11 , wherein a length of the first subarray along the first direction is smaller than the length of the SRAM array.
14. The memory device of claim 13 , wherein a height of the first subarray along the second direction is smaller than the height of the SRAM array.
15. The memory device of claim 11 ,
wherein each n-type transistor in the plurality of first SRAM cells includes a first work function stack,
wherein each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack,
wherein each p-type transistor in the plurality of first SRAM cells includes the second work function stack,
wherein each p-type transistor in the plurality of second SRAM cells includes the first work function stack.
16. The memory device of claim 15 , wherein a thickness of the second work function stack is greater than a thickness of the first work function stack.
17. The memory device of claim 15 ,
wherein the first work function stack includes a titanium aluminum layer
wherein the second work function stack includes at least one titanium nitride layer and the titanium aluminum layer disposed over the at least one titanium nitride layer.
18. A memory device, comprising:
a Static Random Access Memory (SRAM) array comprising:
a first subarray including a plurality of first SRAM cells, and
a second subarray including a plurality of second SRAM cells;
a word line driver coupled to the plurality of first SRAM cells and the plurality of second SRAM cells via a plurality of word lines extending along a first direction; and
a read/write block coupled to the plurality of first SRAM cells and the plurality of second SRAM cells via a plurality of bit lines extending along a second direction perpendicular to the first direction,
wherein each n-type transistor in the plurality of first SRAM cells includes a first work function stack,
wherein each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack,
wherein a word line of the plurality of word lines spans over the first subarray and the second subarray and is electrically coupled to at least one of the plurality of first SRAM cells and at least one of the plurality of second SRAM cells.
19. The memory device of claim 18 ,
wherein each p-type transistor in the plurality of first SRAM cells includes the second work function stack,
wherein each p-type transistor in the plurality of second SRAM cells includes the first work function stack.
20. The memory device of claim 18 ,
wherein the first work function stack includes a titanium aluminum layer,
wherein the second work function stack includes at least one titanium nitride layer and the titanium aluminum layer disposed over the at least one titanium nitride layer.