Display apparatus and method of manufacturing the same
A display apparatus includes a semiconductor layer arranged on a substrate and including a channel area and a source area and a drain area respectively arranged at both sides of the channel area, the semiconductor layer including an opening portion arranged to be adjacent to one of the source area and the drain area, an electrode overlapping in a plan view and electrically connected to one of the source area and the drain area, and an insulating pattern arranged between the semiconductor layer and the electrode, wherein a first edge of the electrode adjacent to the opening portion is spaced apart from the opening portion, and an edge portion of the insulating pattern adjacent to the opening portion is spaced apart from the opening portion.
1 . A display apparatus comprising:
a semiconductor layer arranged on a substrate and including a channel area, and a source area and a drain area respectively arranged at both sides of the channel area, the semiconductor layer including an opening portion arranged to be adjacent to any one of the source area and the drain area;
an electrode overlapping in a plan view and electrically connected to one of the source area and the drain area; and
an insulating pattern arranged between the semiconductor layer and the electrode, wherein
a first edge of the electrode adjacent to the opening portion is spaced apart from the opening portion, and
an edge portion of the insulating pattern adjacent to the opening portion is spaced apart from the opening portion.
2 . The display apparatus of claim 1 , wherein
the insulating pattern includes an inner portion directly below the electrode and the edge portion outside the inner portion, and
the edge portion of the insulating pattern partially surrounds the electrode so as to have a spaced area corresponding to a portion of the first edge of the electrode in a plan view.
3 . The display apparatus of claim 1 , wherein a portion of the semiconductor layer, the portion being directly below the electrode, includes:
a first portion having a carrier concentration corresponding to one of the source area and the drain area; and
a second portion having a different carrier concentration from the first portion.
4 . The display apparatus of claim 2 , wherein
the edge portion of the insulating pattern includes a first portion and a second portion spaced apart from each other with the spaced area below the insulating pattern,
each of the first portion and the second portion extends from the first edge of the electrode in a first direction toward the opening portion, and
each of the first portion and the second portion of the edge portion has a first width in the first direction.
5 . The display apparatus of claim 4 , wherein
the edge portion of the insulating pattern further includes a third portion extending from a second edge of the electrode that is different from the first edge and having a second width, and
the second width is different from the first width.
6 . The display apparatus of claim 5 , wherein the second width is greater than the first width.
7 . The display apparatus of claim 4 , wherein the first width is less than about 0.5 μm.
8 . The display apparatus of claim 1 , further comprising:
a lower conductive layer arranged below the semiconductor layer and a lower insulating layer arranged between the lower conductive layer and the semiconductor layer,
wherein the electrode is electrically connected to the lower conductive layer through a contact hole penetrating the insulating pattern and the lower insulating layer.
9 . The display apparatus of claim 1 , wherein the semiconductor layer includes an oxide semiconductor material.
10 . The display apparatus of claim 1 , wherein the electrode is provided as a triple layer including a conductive oxide.
11 . A method of manufacturing a display apparatus, the method comprising:
forming a semiconductor layer on a substrate, the semiconductor layer including a channel area, and a source area and a drain area respectively arranged at both sides of the channel area;
forming, in the semiconductor layer, an opening portion arranged to be adjacent to one of the source area and the drain area;
forming an electrode overlapping in a plan view and electrically connected to one of the source area and the drain area; and
forming an insulating pattern by etching an inorganic insulating layer arranged between the semiconductor layer and the electrode, wherein
a first edge of the electrode adjacent to the opening portion is spaced apart from the opening portion, and
an edge portion of the insulating pattern adjacent to the opening portion is spaced apart from the opening portion.
12 . The method of claim 11 , wherein
the forming of the semiconductor layer including the source area and the drain area includes:
forming a preliminary semiconductor layer on the substrate;
patterning the preliminary semiconductor layer into a semiconductor layer;
forming an inorganic insulating layer on the patterned semiconductor layer;
forming holes by at least partially etching the inorganic insulating layer, and
when the holes are formed, an exposed portion of the semiconductor layer becomes conductive.
13 . The method of claim 11 , wherein the forming of the opening portion is simultaneously performed with the forming of the insulating pattern.
14 . The method of claim 11 , wherein the forming of the electrode includes:
forming a preliminary electrode layer on the inorganic insulating layer;
forming a photoresist on the preliminary electrode layer;
etching the preliminary electrode layer; and
removing the photoresist.
15 . The method of claim 14 , wherein
the forming of the opening portion includes etching the preliminary electrode layer, and
when the preliminary electrode layer is etched, a portion of the semiconductor layer is removed.
16 . The method of claim 14 , wherein
the photoresist includes:
a central portion having a first thickness; and
an edge portion of at least one side surface, the edge portion having a second thickness, and
the second thickness is less than the first thickness.
17 . The method of claim 14 , wherein the forming of the photoresist includes:
applying a photoresist layer; and
exposing an edge of at least one side surface of the photoresist layer by using a halftone mask or a slit.
18 . The method of claim 16 , wherein the edge portion of the at least one side surface of the photoresist includes an edge portion of a side surface of the photoresist, the side surface being toward the channel area of the semiconductor layer.
19 . The method of claim 16 , wherein
the forming of the insulating pattern includes:
forming the inorganic insulating layer on the semiconductor layer;
etching the photoresist; and
etching the inorganic insulating layer, and
when the photoresist is etched, the edge portion having the second thickness is removed.
20 . The method of claim 11 , wherein the semiconductor layer includes an oxide semiconductor.