Device scaling by isolation enhancement
A device includes a gate electrode and a gate dielectric surrounding the gate electrode. The gate electrode surrounds a nanostructure. The nanostructure includes stacked nanosheets. The gate dielectric is formed by a high-k (HK) material. The HK material covers sidewalls of the gate electrode in a direction aligned to adjacent devices. Portions of the HK material are recessed from the sidewalls and refilled by a dielectric material with a dielectric constant less than the HK material and an electrical isolation capability greater than the HK material. Replacing the HK material over the sidewalls of the gate electrode with the dielectric material enhances electrical isolation between the gate electrode with adjacent contacts. Consequently, it can reduce electrical leakage between metal gate (MG) contacts and metal-to-device (MD) contacts in scaled transistors of an integrated circuit (IC).
1 . A method, comprising:
forming a channel region of a transistor, the channel region including a plurality of semiconductor nanostructures overlying and spaced apart from one another;
forming a first dielectric layer on the channel region;
forming a gate electrode on the channel region, the gate electrode having first and second sidewalls opposite one another;
forming a first spacer on the first dielectric layer by removing a portion of a first spacer layer, the first dielectric layer extending laterally between the first spacer and the first sidewall of the gate electrode;
forming a second spacer on the first dielectric layer by removing a portion of a second spacer layer, the first dielectric layer extending laterally between the second spacer and the second sidewall of the gate electrode;
forming a plurality of recesses by removing the portion of the first spacer layer and removing the portion of the second spacer layer exposing respective surfaces of a plurality of source/drain regions, an interlayer dielectric layer, and a first liner layer between the plurality of source/drain regions and the interlayer dielectric layer;
forming a second liner layer on the first liner layer, on the interlayer dielectric layer, on the one or more source/drain regions, and on the first sidewall and the second sidewall of the gate electrode, forming the second liner layer includes partially filling the plurality of recesses; and
forming a second dielectric layer on the second liner layer filling respective remaining portions of the plurality of recesses.
2 . The method of claim 1 , further comprising:
forming the one or more source/drain regions at one or more regions adjacent to one or more isolation trenches extending into a substrate.
3 . The method of claim 2 ,
wherein forming the one or more source/drain regions includes forming one or more concave surfaces of the one or more source/drain regions.
4 . The method of claim 1 , wherein forming the channel region of the transistor includes forming the plurality of semiconductor nanostructures overlying and spaced apart from one another.
5 . The method of claim 1 , further comprising, before forming the first dielectric layer, forming a third dielectric layer the channel region, and wherein the first dielectric layer is formed on the channel region, and the third dielectric extends from the channel region to the first dielectric layer.
6 . The method of claim 5 , wherein forming the channel region of the transistor includes forming the plurality of semiconductor nanostructures overlying and spaced apart from one another, wherein forming the gate electrode includes forming the gate electrode extending between the semiconductor nanostructures.
7 . The method of claim 1 , wherein the first dielectric layer is selected from ZrAlO, TiO, TaO, ZrO, LaO, HfO, AlO, YO, ZnO, and HZO.
8 . A method, comprising:
forming a channel region of a transistor, the channel region including one or more semiconductor nanostructures;
forming one or more dielectric layers on the channel region;
forming a gate electrode at least partially surrounding the one or more semiconductor nanostructures;
and on the one or more dielectric layers, the one or more dielectric layers including a high-k dielectric layer between the channel region and the gate electrode, and the high-k dielectric layer is on a first sidewall of the gate electrode and a second sidewall of the gate electrode opposite to the first sidewall;
forming a first spacer abutting the high-k dielectric layer by removing a portion of a first spacer layer, the high-k dielectric layer extending laterally between the first spacer and the first sidewall of the gate electrode;
forming a second spacer abutting the high-k dielectric layer by removing a portion of the second spacer layer, the high-k dielectric layer extending laterally between the second spacer and the second sidewall of the gate electrode;
forming one or more recesses by removing the portion of the first spacer layer and by removing the portion of the second spacer layer exposing respective surfaces of one or more source/drain regions, an interlayer dielectric layer, and a first liner layer between the one or more source/drain regions and the interlayer dielectric layer;
forming a dielectric liner layer in and partially filling the one or more recesses, on the one or more source/drain regions, and on the first sidewall and the second sidewall of the gate electrode, wherein the second liner layer has a dielectric constant less than a dielectric constant of the high-k dielectric layer of the one or more dielectric layers; and
forming a second dielectric layer on the second liner layer filling respective remaining portions of the one or more recesses.
9 . The method of claim 8 , further comprising
planarizing respective surfaces of the gate electrode, the second liner layer, and the second dielectric layer.
10 . The method of claim 8 , wherein forming the one or more dielectric layers includes performing a plasma etching process having a precursor including carbon, hydrogen, and fluorine, and having a bias voltage of less than 10 volts.
11 . The method of claim 10 ,
wherein forming the one or more dielectric layers includes plasma etching the high-k dielectric layer of the one or more dielectric layers.
12 . The method of claim 8 , wherein the high-k dielectric layer is selected from ZrAlO, TiO, TaO, ZrO, LaO, HfO, AlO, YO, ZnO, and HZO.
13 . The method of claim 8 , wherein forming the one or more dielectric layers further includes forming an interfacial dielectric layer on the channel region and forming the high-k dielectric layer on the interfacial dielectric layer, and the interfacial dielectric layer having a dielectric constant less than the dielectric constant of the high-k dielectric layer.
14 . The method of claim 8 , wherein forming the one or more semiconductor nanostructures of the channel region includes forming a plurality of semiconductor nanosheets stacked one above another.
15 . The method of claim 14 wherein forming the gate electrode includes forming the gate electrode to at least partially surround each of the semiconductor nanosheets.
16 . A method, comprising:
forming a plurality of semiconductor nanostructures of a plurality of channel regions spaced apart from one another over a semiconductor substrate;
forming a gate electrode on the plurality of semiconductor nanostructures of the plurality of channel regions, the gate electrode having a first sidewall and a second sidewall opposite to the first sidewall;
forming a first dielectric layer between the gate electrode and each of the plurality of channel regions;
forming a first spacer by removing a portion of a first spacer layer adjacent the first sidewall of the gate electrode and a second spacer by removing a portion of a second spacer layer adjacent the second sidewall of the gate electrode, the first dielectric layer extending laterally between first spacer and the first sidewall of the gate electrode, and the first dielectric layer extending laterally between the second spacer and the second sidewall of the gate electrode;
forming a plurality of recesses by removing the portion of the first spacer layer and by removing the portion of the second spacer layer exposing respective surfaces of a plurality of source/drain regions, an interlayer dielectric layer, and a first liner layer between the plurality of source/drain regions and the interlayer dielectric layer;
forming a second liner layer in the plurality of recesses, on the plurality of source/drain regions, and on the first sidewall and the second sidewall of the gate electrode, and wherein the second dielectric liner layer having a dielectric constant less than the dielectric constant of the first dielectric layer; and
forming a second dielectric layer on the second liner layer and in the plurality of recesses.
17 . The method of claim 16 , further comprising planarizing respective surfaces of the gate electrode, the second liner layer, and the second dielectric layer.
18 . The method of claim 16 , further comprising forming an interfacial layer between the first dielectric layer and each of the plurality of channel regions, the interfacial layer having a dielectric constant less than the dielectric constant of the first dielectric layer.
19 . The method of claim 16 , wherein the first dielectric layer comprises a high-k material selected from ZrAlO, TiO, TaO, ZrO, LaO, HfO, AlO, YO, ZnO, and HZO.
20 . The method of claim 16 , further comprising removing one or more portions of the first dielectric layer by performing a plasma etch using a precursor containing carbon, hydrogen, and fluorine at a bias voltage of less than 10 volts.