FORMATION OF MEMORY DIE AND LOGIC DIE WITH WAFER-ON-WAFER BOND
Methods, systems, and devices related to forming a wafer-on-wafer bond between a memory die and a logic die. A plurality of first metal pads can be formed on a first wafer and a plurality of second metal pads can be formed on a second wafer. A subset of the first metal pads can be bonded to a subset of the second metal pads via a wafer-on-wafer bonding process. Each of a plurality of memory devices on the first wafer can be aligned with and coupled to at least a respective one of a plurality of logic devices on the second wafer. The bonded first and second wafers can be singulated into individual wafer-on-wafer bonded memory and logic dies.
1 . A method, comprising:
forming a plurality of first metal pads on a first wafer;
forming a plurality of second metal pads on a second wafer;
bonding, via a wafer-on-wafer bonding process, a subset of the first metal pads to a subset of the second metal pads such that each of a plurality of memory devices on the first wafer is aligned with and coupled to at least a respective one of a plurality of logic devices on the second wafer; and
singulating the bonded first and second wafers into individual wafer-on-wafer bonded memory and logic dies.
2 . The method of claim 1 , further comprising, prior to bonding the subset of the first metal pads to the subset of the second metal pads, forming the plurality of memory devices on the first wafer.
3 . The method of claim 1 , further comprising, prior to bonding the subset of the first metal pads to the subset of the second metal pads, forming the plurality of logic devices on the second wafer.
4 . The method of claim 1 , wherein bonding the subset of the first metal pads to the subset of the second metal pads comprises coupling a respective input/output (IO) line of each of the plurality of memory devices to an IO line of a respective one of the plurality of logic devices.
5 . The method of claim 1 , wherein forming the plurality of first metal pads comprises forming memory-to-logic circuitry on the plurality of memory devices.
6 . The method of claim 5 , wherein forming the memory-to-logic circuitry further comprises coupling a plurality of local input/output (LIO) lines of the memory devices to the subset of the first metal pads and to a different subset of the first metal pads,
wherein the subset of the first metal pads are dedicated to communication between the plurality of memory devices and the plurality of logic devices via the memory-to-logic circuitry, and
wherein the different subset of the first metal pads are dedicated to communication external to the wafer-on-wafer bonded memory dies and logic dies.
7 . The method of claim 1 , wherein forming the plurality of second metal pads comprises forming logic-to-memory circuitry on the plurality of logic devices.
8 . The method of claim 1 , wherein bonding the subset of the first metal pads to the subset of the second metal pads comprises bonding such that four of the plurality of memory devices on the first wafer are aligned with and coupled to a respective one of the plurality of logic devices on the second wafer,
wherein four of the plurality of memory devices and one of the plurality of logic devices have a same footprint.
9 . A method, comprising:
forming a wafer-on-wafer bond between a first wafer having a memory die formed thereon and a second wafer having a logic die formed thereon,
wherein the memory die comprises a memory array and a plurality of input/output (IO) lines coupled thereto, and
wherein forming the wafer-on-wafer bond comprises:
providing a plurality of data paths from the memory die directly to the logic die, and
coupling the plurality of IO lines to a deep learning accelerator (DLA) formed on the logic die.
10 . The method of claim 9 , further comprising, prior to forming the wafer-on-wafer bond, positioning the first wafer and the second wafer such that the memory die and the logic die are in a face-to-face arrangement; and
forming the wafer-on-wafer bond such that the memory die and the logic die remain in the face-to-face arrangement.
11 . The method of claim 9 , wherein forming the wafer-on-wafer bond comprises forming a metal material in contact with the memory die and the logic die.
12 . The method of claim 11 , wherein forming the wafer-on-wafer bond further comprises annealing the metal material.
13 . The method of claim 11 , wherein forming the wafer-on-wafer bond further comprises bonding the metal material to the memory die and the logic die at room temperature.
14 . The method of claim 9 , wherein forming the wafer-on-wafer bond comprises bonding a first metal material of the logic die to a second metal material of the memory die.
15 . The method of claim 14 , wherein bonding the first metal material and the second metal material comprises merging, via a thermal process, the first metal material and the second metal material into a third metal material in contact with the memory die and the logic die.
16 . A method, comprising:
forming, on a substrate, a logic die comprising a deep learning accelerator (DLA) thereon, wherein the DLA is distinct from other circuitry of the logic die;
communicatively coupling, in a face-to-face arrangement, a first memory die to the DLA, wherein the first memory die has a more preferred value of a performance metric; and
communicatively coupling, in the face-to-face arrangement, a second memory die to the other circuitry of the logic die, wherein the second memory die has a less preferred value of the performance metric.
17 . The method of claim 16 , further comprising, prior to communicatively coupling the first and second memory dies:
determining that the first memory die has the more preferred value; and
determining that the second memory die has the less preferred value.
18 . The method of claim 17 , further comprising:
communicatively coupling the first memory die to the DLA in response to determining that the first memory die has the more preferred value; and
communicatively coupling the second memory die to the other circuitry of the logic die in response to determining that the second memory die has the less preferred value.
19 . The method of claim 17 , further comprising selecting the first and second memory dies from a pool of memory dies.
20 . A method, comprising:
forming a plurality of memory devices on a first wafer;
forming a plurality of logic devices on a second wafer; and
forming a wafer-on-wafer bond, wherein forming the wafer-on-wafer bond:
couples memory-to-logic circuitry formed on the plurality of memory devices to the plurality of logic devices; and
provides a plurality of data paths dedicated for communication of data between the memory-to-logic circuitry to the plurality of logic devices.
21 . The method of claim 20 , wherein forming the wafer-on-wafer bond comprises aligning a plurality of pads of the second wafer coupled to the plurality of logic devices with a plurality of transceivers of the first wafer.
22 . The method of claim 20 , wherein forming the wafer-on-wafer bond comprises forming a metal material in contact with the plurality of memory devices and the plurality of logic devices.
23 . A method, comprising:
bonding a stack of memory dies to a substrate, wherein the stack of memory dies comprises a respective first memory die proximal to the substrate and a respective last memory die distal to the substrate; and
bonding a logic die to the substrate with a plurality of bump contacts in-plane with the stack of memory dies, wherein the logic die is in contact with the respective last memory die.
24 . The method of claim 23 , further comprising forming the plurality of bump contacts as a ball grid array (BGA) on the substrate.
25 . The method of claim 23 , wherein bonding the stack of memory dies and bonding the logic die comprises:
bonding a first surface of the respective last memory die to another memory die of the stack of memory dies; and
bonding a second surface of the respective last memory die, opposite the first surface, to the logic die.