MEMORY DIE AND LOGIC DIE WITH WAFER-ON-WAFER BOND
Methods, systems, and devices related to a memory die and a logic die having a wafer-on-wafer bond therebetween. A memory die can include a memory array and a plurality of input/output (IO) lines coupled thereto. A logic die can include to a deep learning accelerator (DLA). The memory die can be coupled to the logic die by a wafer-on-wafer bond. The wafer-on-wafer bond can couple the plurality of IO lines to the DLA.
1 . An apparatus, comprising:
a substrate;
a memory die coupled to the substrate and comprising a plurality of memory devices; and
a logic die coupled to the memory die by a wafer-on-wafer bond and comprising to a plurality of logic devices, wherein at least one of the plurality of logic devices comprises a deep learning accelerator (DLA), and
wherein the wafer-on-wafer bond couples at least one of the plurality of memory devices directly to the DLA.
2 . The apparatus of claim 1 , wherein the memory die and the logic die are in a face-to-face arrangement.
3 . The apparatus of claim 1 , wherein the wafer-on-wafer bond comprises a metal material formed in contact with the memory die and the logic die.
4 . The apparatus of claim 1 , wherein the memory die further comprises a plurality of global input/output (IO) lines coupled to a plurality of local IO lines of the plurality of memory devices, and
wherein the wafer-on-wafer bond couples the plurality of global IO lines directly to the DLA.
5 . The apparatus of claim 4 , wherein the logic die comprises a plurality of pads, and
wherein the wafer-on-wafer bond couples respective ones of the plurality of global IO lines to the plurality of pads.
6 . The apparatus of claim 1 , wherein the wafer-on-wafer bond is further configured to communicate data values from at least one of the plurality of memory devices to the DLA in parallel.
7 . The apparatus of claim 1 , wherein the wafer-on-wafer bond comprises a first metal material of the logic die and a second metal material of the memory die.
8 . The apparatus of claim 1 , wherein the memory die further comprises memory-to-logic circuitry configured to provide paths for communication of data values from the plurality of memory devices directly to the DLA.
9 . The apparatus of claim 8 , wherein the wafer-on-wafer bond is in contact with the memory-to-logic circuitry.
10 . The apparatus of claim 1 , wherein the logic die further comprises logic-to-memory circuitry configured to:
receive first data values directly from the plurality of memory devices;
provide the first data values to the DLA; and
provide second data values from the DLA to the plurality of memory devices.
11 . The apparatus of claim 10 , wherein the wafer-on-wafer bond is in contact with the logic-to-memory circuitry.
12 . The apparatus of claim 1 , wherein the apparatus comprises a digital signal processor (DSP), a graphics processing unit (GPU), or a system on chip (SoC).
13 . The apparatus of claim 1 , wherein the logic die comprises a plurality of vias directly coupled to the wafer-on-wafer bond.
14 . The apparatus of claim 1 , wherein the plurality of memory devices comprise dynamic random-access memory (DRAM) devices.
15 . An apparatus, comprising:
a substrate;
a logic die coupled to the substrate, wherein the logic die comprises a deep learning accelerator (DLA), wherein the DLA is distinct from other circuitry of the logic die;
a first memory die coupled to the DLA in a face-to-face arrangement, wherein the first memory die has a more preferred value of a performance metric; and
a second memory die coupled to the other circuitry of the logic die in the face-to-face arrangement, wherein the second memory die has a less preferred value of the performance metric
16 . The apparatus of claim 15 , wherein the first memory die comprises:
a memory device; and
a plurality of input/output (IO) lines coupled to the memory device to communicate data values from the memory device to an external destination, and
a plurality of data paths dedicated to communication between the memory device and the DLA.
17 . The apparatus of claim 16 , wherein the other circuitry of the logic die is configured to direct all signaling from the first memory die to the external destination.
18 . An apparatus, comprising:
a substrate;
a stack of memory dies bonded to the substrate, wherein the stack of memory dies comprises a respective first memory die proximal to the substrate and a respective last memory die distal to the substrate and bonded to the substrate; and
a logic die bonded to the substrate with a plurality of bump contacts in-plane with the stack of memory dies, wherein the logic die is in contact with the respective last memory die.
19 . The apparatus of claim 18 , wherein the plurality of bump contacts comprise a ball grid array (BGA) on the substrate.
20 . The apparatus of claim 18 , wherein a first surface of the respective last memory die is bonded to another memory die of the stack of memory dies, and
wherein a second surface of the respective last memory die, opposite the first surface, is bonded to the logic die.