3D stacked die test architecture
This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.
1. A device comprising:
a bottom surface;
a top surface opposite the bottom surface;
an improved test access port (ITAP) circuit including:
a test data in (TDI) input coupled to a TDI input pad on the bottom surface;
a test clock (TCK) input coupled to a TCK input pad on the bottom surface;
a test mode select (TMS) input coupled to a TMS input pad on the bottom surface;
a capture (CPT) input coupled to a CPT input pad on the bottom surface;
a test data out (TDO) output coupled to a TDO output pad on the top surface; and
control outputs;
a first signaling path formed between the TCK input pad on the bottom surface and a TCK output pad on the top surface;
a second signaling path formed between the CPT input pad on the bottom surface and a CPT output pad on the top surface;
gating circuitry including:
a gating input coupled to the TMS input pad on the bottom surface;
a gating output coupled to a TMS output pad on the top surface; and
a gating control input coupled to one of the control outputs of the ITAP circuit;
multiplexer circuitry including:
a first input coupled to the TDO output of the ITAP;
a second input coupled to a TDI input pad on the top surface;
an output coupled to a TDO output pad on the bottom surface; and
a multiplexer control input coupled to one of the control outputs of the ITAP circuit; and
a plurality (N) of parallel test data in (PTDI) input and PTDI output pad pairs that include a plurality (N) of PTDI input pads on the bottom surface coupled to a corresponding plurality (N) of PTDI output pads on the top surface; and
a plurality (N) of PTDO input and PTDO output pad pairs that include a plurality (N) of PTDO input pads on the top surface coupled to a corresponding plurality (N) of PTDO output pads on the bottom surface.
2. The device of claim 1 , further comprising:
scan test circuitry that includes scan inputs coupled to the N or less than the N of the PTDI input pads of the bottom surface;
scan outputs coupled to the N or less than the N of the PTDO output pads of the bottom surface; and
at least one of a plurality of control inputs of the ITAP coupled to at least one of a plurality of control outputs of the ITAP.
3. The device of claim 2 , wherein:
the scan test circuitry includes a test compression circuit.
4. The device of claim 2 , further comprising:
a plurality of three-state buffers coupled to the scan outputs, wherein each of the plurality of three-state buffers is configured to respond to respective buffer control inputs from at least one of the plurality of control outputs of the ITAP to selectively enable or disable the scan outputs to drive the PTDO output pads.
5. The device of claim 4 , further comprising:
a first three-state buffer of the plurality of three-state buffers configured to enable a first scan output to drive a first PTDO output pad; and
a second three-state buffer of the plurality of three-state buffers configured to disable a second scan output from driving a second PTDO output pad.
6. The device of claim 1 , further comprising:
first scan test circuitry including:
first scan inputs coupled to the N or less than the N of the PTDI input pads of the bottom surface; and
first scan outputs coupled to the N or less than the N of the PTDO output pads of the bottom surface;
second scan test circuitry including:
second scan inputs coupled to the N or less than the N of the PTDI input pads of the bottom surface; and
second scan outputs coupled to the N or less than the N of the PTDO output pads of the bottom surface; and
at least one of a plurality of control inputs of the ITAP coupled to at least one of a plurality of control outputs of the ITAP.
7. The device of claim 6 , wherein:
the first scan test circuitry includes a first test compression circuit; and
the second scan test circuitry includes a second test compression circuit.
8. The device of claim 6 , further comprising:
a first plurality of three-state buffers coupled to the first scan outputs of the first scan test circuitry, wherein the first plurality of three-state buffers is configured to respond to a first buffer control input from one of the plurality of the control outputs of the ITAP to selectively enable or disable the first scan outputs to drive the PTDO output pads, and
a second plurality of three-state buffers coupled to the second scan outputs of the second scan test circuitry, wherein the second plurality of three-state buffers is configured to respond to a second buffer control input from one of the plurality of the control outputs of the ITAP to selectively enable or disable the second scan outputs to drive the PTDO output pads.
9. A device comprising:
a bottom surface;
a top surface opposite the bottom surface;
an improved test access port (ITAP) circuit including:
a test data in (TDI) input coupled to a TDI input pad on the bottom surface;
a test clock (TCK) input coupled to a TCK input pad on the bottom surface;
a test mode select (TMS) input coupled to a TMS input pad on the bottom surface;
a capture (CPT) input coupled to a CPT input pad on the bottom surface;
a test data out (TDO) output coupled to a TDO output pad on the top surface;
an update (UPD) input coupled to an UDP input pad on the bottom surface;
a TDO output coupled to a TDO output pad on the top surface; and
control outputs;
a first signaling path formed between the TCK input pad on the bottom surface and a TCK output pad on the top surface;
a second signaling path formed between the CPT input pad on the bottom surface and a CPT output pad on the top surface;
a third signaling path formed between the UPD input pad of the bottom surface and an UPD output pad on the top surface;
gating circuitry including:
a gating input coupled to the TMS input pad on the bottom surface;
a gating output coupled to a TMS output pad on the top surface; and
a gating control input coupled to one of the control outputs of the ITAP circuit;
multiplexer circuitry including:
a first input coupled to the TDO output of the ITAP;
a second input coupled to a TDI input pad on the top surface;
an output coupled to a TDO output pad on the bottom surface; and
a multiplexer control input coupled to one of the control outputs of the ITAP circuit; and
a plurality (N) of parallel test data in (PTDI) input and PTDI output pad pairs that include a plurality (N) of PTDI input pads on the bottom surface coupled to a corresponding plurality (N) of PTDI output pads on the top surface; and
a plurality (N) of PTDO input and PTDO output pad pairs that include a plurality (N) of PTDO input pads on the top surface coupled to a corresponding plurality (N) of PTDO output pads on the bottom surface.
10. The device of claim 9 , further comprising:
scan test circuitry that includes scan inputs coupled to N or less than N of the PTDI input pads of the bottom surface;
scan outputs coupled to N or less than N of the PTDO output pads of the bottom surface; and
at least one of a plurality of control inputs of the ITAP coupled to at least one of a plurality of control outputs of the ITAP.
11. The device of claim 10 , wherein:
the scan test circuitry includes a test compression circuit.
12. The device of claim 10 , further comprising:
a plurality of three-state buffers coupled to the scan outputs, wherein the plurality of three-state buffers is configured to respond to respective buffer control inputs from at least one of the plurality of control outputs of the ITAP to selectively enable or disable the scan outputs to drive the PTDO output pads.
13. The device of claim 12 , further comprising:
a first three-state buffer of the plurality of three-state buffers configured to enable a first scan output to drive a first PTDO output pad; and
a second three-state buffer of the plurality of three-state buffers configured to disable a second scan output from driving a second PTDO output pad.
14. The device of claim 9 , further comprising:
first scan test circuitry including:
first scan inputs coupled to the N or less than the N of the PTDI input pads of the bottom surface; and
first scan outputs coupled to the N or less than the N of the PTDO output pads of the bottom surface;
second scan test circuitry including:
second scan inputs coupled to the N or less than the N of the PTDI input pads of the bottom surface; and
second scan outputs coupled to the N or less than the N of the PTDO output pads of the bottom surface; and
at least one of a plurality of control inputs of the ITAP coupled to at least one of a plurality of control outputs of the ITAP.
15. The device of claim 14 , wherein:
the first scan test circuitry includes a first test compression circuit; and
the second scan test circuitry includes a second test compression circuit.
16. The device of claim 14 , further comprising:
a first plurality of three-state buffers coupled to the first scan outputs of the first scan test circuitry, wherein the first plurality of three-state buffers is configured to respond to a first buffer control input from one of the plurality of the control outputs of the ITAP to selectively enable or disable the first scan outputs to drive the PTDO output pads, and
a second plurality of three-state buffers coupled to the second scan outputs of the second scan test circuitry, wherein the second plurality of three-state buffers is configured to respond to a second buffer control input from one of the plurality of the control outputs of the ITAP to selectively enable or disable the second scan outputs to drive the PTDO output pads.