High band-gap devices with a doped high band-gap gate electrode extension
A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of p-type GaN semiconductor material. The GaN FET includes a gate electrode extension of p-type GaN semiconductor material in electrical contact with the gate electrode. The gate electrode extension of p-type GaN semiconductor material in electrical contact with the gate electrode may improve the GaN FET characteristics such as off state leakage, subthreshold voltage and post stress Vt shift.
1 . A microelectronic device, comprising:
a gallium nitride field effect transistor (GaN FET), including:
a channel layer of III-N material;
a barrier layer of III-N material over the channel layer;
a p-type GaN layer on the barrier layer;
a gate metal layer on the p-type GaN layer;
a gate including a first portion of the p-type GaN layer and a first portion of the gate metal layer on the first portion of the p-type GaN layer; and
a p-type GaN gate electrode extension including a second portion of the p-type GaN layer and a second portion of the gate metal layer on the second portion of the p-type GaN layer, wherein,
the second portion of the p-type GaN layer is contiguous to the first portion of the p-type GaN layer, and the second portion of the gate metal layer is contiguous to the first portion of the gate metal laver; and
the p-type GaN gate electrode extension extends beyond the gate, but is inside of an isolation region laterally surrounding the GaN FET.
2 . The microelectronic device of claim 1 , wherein the GaN FET includes a high bandgap layer of III-N semiconductor material between the channel layer and the barrier layer.
3 . The microelectronic device of claim 1 , wherein the p-type GaN gate electrode extension is under a gate electrode bond pad of the GaN FET.
4 . The microelectronic device of claim 1 , wherein the GaN FET includes an etch stop layer disposed over the barrier layer.
5 . The microelectronic device of claim 1 , wherein the gate metal layer forms a Schottky contact on the p-type GaN laver.
6 . The microelectronic device of claim 1 , wherein the GaN FET is an enhanced mode transistor.
7 . The microelectronic device of claim 1 , wherein the GaN FET is a depletion mode transistor.
8 . The microelectronic device of claim 1 , wherein the isolation region includes an amorphous region of the barrier layer.
9 . The microelectronic device of claim 1 , wherein the isolation region is free of the barrier layer.
10 . The microelectronic device of claim 1 , wherein:
the gate of the GaN FET includes a first dimension extending between a source of the GaN FET and a drain of the GaN FET; and
the p-type GaN gate electrode extension includes a second dimension parallel to the first dimension, the second dimension greater than the first dimension.
11 . A method of forming a microelectronic device with a gallium nitride field effect transistor (GaN FET), comprising:
forming a channel layer of III-N semiconductor material;
forming a barrier layer of III-N semiconductor material over the channel layer;
forming a p-type GaN layer over the barrier layer;
forming a gate metal layer on the p-type GaN layer;
forming an isolation region encircling the GaN FET; and
patterning the gate metal layer and the p-type GaN layer to form a gate of the GaN FET and a p-type GaN gate electrode extension contiguous to the gate, wherein:
the gate includes a first portion of the p-type GaN layer and a first portion of the gate metal layer; and
the p-type GaN gate electrode extension extends beyond the gate, but is inside of the isolation region, the p-type GaN gate electrode extension including a second portion of the p-type GaN layer contiguous to the first portion of the p-type GaN layer and a second portion of the gate metal layer contiguous to the first portion of the gate metal layer.
12 . The method of claim 11 , further including forming a high bandgap layer of III-N semiconductor material between the channel layer and the barrier layer.
13 . The method of claim 11 , wherein the p-type GaN gate electrode extension is under a gate electrode bond pad of the GaN FET.
14 . The method of claim 11 , further including forming an etch stop layer over the barrier layer.
15 . The method of claim 11 , wherein the gate metal layer forms a Schottky contact to the p-type GaN layer.
16 . The method of claim 11 , wherein the GaN FET is an enhanced mode transistor.
17 . The method of claim 11 , wherein the GaN FET is a depletion mode transistor.
18 . The method of claim 11 , wherein the isolation region includes an amorphous region of the barrier layer.
19 . The method of claim 11 , wherein the isolation region is formed free of the barrier layer.
20 . The method of claim 11 , wherein:
the gate of the GaN FET includes a first dimension extending between a source of the GaN FET and a drain of the GaN FET; and
the p-type GaN gate electrode extension includes a second dimension parallel to the first dimension, the second dimension greater than the first dimension.