IP Library › Granted Patent US 11,798,491
Granted Patent B2
US 11,798,491 · App. 17/887,708 · Granted Oct 24, 2023

Display device and electronic device

Inventors: Takayuki Ikeda (Atsugi, JP); Hidetomo Kobayashi (Isehara, JP); Hideaki Shishido (Atsugi, JP); Kiyotaka Kimura (Isehara, JP); Takashi Nakagawa (Sagamihara, JP); Kosei Nei (Yokohama, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G09G3/3275G09G3/3233G09G3/3266G09G5/377H01L29/7869H10K59/1275G09G3/36G09G2300/0426G09G2300/0809G09G2310/0297G09G2340/12
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,798,491
App. No.
17/887,708
Granted
Oct 24, 2023
Kind
B2
Abstract

A high-definition display device is provided. A small display device is provided. In the display device, a first layer and a second layer are stacked and provided. The first layer includes a gate driver circuit and a source driver circuit, and the second layer includes a display portion. The gate driver circuit and the source driver circuit are provided to include a region overlapping with the display portion. The gate driver circuit and the source driver circuit have an overlap region where they are not strictly separated from each other. Five or more gate driver circuits and five or more source driver circuits can be provided.

Claims (55)

1. A display device comprising:

a first layer; and

a second layer,

wherein the first layer and the second layer are stacked,

wherein the first layer includes a gate driver circuit and a source driver circuit,

wherein the second layer includes a display portion,

wherein pixels are arranged in a matrix in the display portion,

wherein the gate driver circuit and the source driver circuit each include a first region overlapping with the display portion,

wherein the gate driver circuit and the source driver circuit share a second region,

wherein the gate driver circuit comprises first and second transistors in the second region, and

wherein the source driver circuit comprises a third transistor positioned between the first and second transistors in the second region.

2. The display device according to claim 1 ,

wherein the first layer comprises a transistor including silicon, and

wherein the second layer comprises a transistor including a metal oxide in a channel formation region.

3. The display device according to claim 1 ,

wherein the pixel includes a display element, and

wherein the display element is a light-emitting element.

4. A display device comprising:

a first layer; and

a second layer,

wherein the first layer and the second layer are stacked,

wherein the first layer includes a first gate driver circuit, a second gate driver circuit, a first source driver circuit, and a second source driver circuit,

wherein the second layer includes a first display portion and a second display portion,

wherein pixels are arranged in a matrix in the first display portion,

wherein pixels are arranged in a matrix in the second display portion,

wherein the first gate driver circuit and the first source driver circuit each include a first region overlapping with the first display portion,

wherein the second gate driver circuit and the second source driver circuit each include a second region overlapping with the second display portion,

wherein the first gate driver circuit and the first source driver circuit share a third region,

wherein the second gate driver circuit and the second source driver circuit share a fourth region,

wherein the first gate driver circuit comprises first and second transistors in the third region, and

wherein the first source driver circuit comprises a third transistor positioned between the first and second transistors in the third region.

5. The display device according to claim 4 ,

wherein the first layer comprises a transistor including silicon, and

wherein the second layer comprises a transistor including a metal oxide in a channel formation region.

6. The display device according to claim 4 ,

wherein the pixel includes a display element, and

wherein the display element is a light-emitting element.

7. A display device comprising:

a first layer; and

a second layer,

wherein the first layer and the second layer are stacked,

wherein the first layer includes a gate driver circuit, a first source driver circuit, and a second source driver circuit,

wherein the second layer includes a display portion,

wherein pixels are arranged in a matrix in the display portion,

wherein the gate driver circuit, the first source driver circuit, and the second source driver circuit each include a first region overlapping with the display portion,

wherein the gate driver circuit and the first source driver circuit share a second region,

wherein the gate driver circuit and the second source driver circuit share a third region,

wherein the gate driver circuit comprises first and second transistors in the second region, and

wherein the first source driver circuit comprises a third transistor positioned between the first and second transistors in the second region.

8. The display device according to claim 7 ,

wherein the first layer comprises a transistor including silicon, and

wherein the second layer comprises a transistor including a metal oxide in a channel formation region.

9. The display device according to claim 7 ,

wherein the pixel includes a display element, and

wherein the display element is a light-emitting element.

Priority Claims (3)
JP 2018-095244 · May 17, 2018 · national
JP 2018-108416 · Jun 6, 2018 · national
JP 2018-159543 · Aug 28, 2018 · national
Continuity (2)
Continuation 17055285
Related Publication 20230022181A1 · Jan 26, 2023
Cited By (6)
US 12,243,492 US 12,455,446 US 12,488,752 US 12,499,828 US 12,555,529 US 12,682,818