Error log indication via error control information
Methods, systems, and devices for error log indication via error control information are described. For instance, a memory device may transmit, to a host device, a first signal including a set of error control bits indicating that an error log of the memory device includes information for use by the host device. The memory device may receive, from the host device in response to the first signal, a second signal including a request to retrieve the information of the error log. The memory device may transmit, to the host device in response to the second signal, a third signal including the information of the error log.
1. A method, comprising:
transmitting, to a host device, a first signal comprising a set of error control bits indicating that an error log of a memory device comprises information for use by the host device;
receiving, from the host device in response to the first signal, a second signal comprising a request to retrieve the information of the error log; and
transmitting, to the host device in response to the second signal, a third signal comprising the information of the error log.
2. The method of claim 1 , further comprising:
determining a second set of error control bits based at least in part on data retrieved from the memory device; and
transforming the second set of error control bits into the set of error control bits based at least in part on the error log comprising the information, wherein transmitting the first signal that comprises the set of error control bits is based at least in part on transforming the second set of error control bits into the set of error control bits.
3. The method of claim 2 , further comprising:
determining that the error log includes the information for use by the host device, wherein transforming the second set of error control bits into the set of error control bits is based at least in part on the determining.
4. The method of claim 2 , further comprising:
determining that the second set of error control bits comprises an invalid error control code, wherein transforming the second set of error control bits into the set of error control bits is based at least in part on the determining.
5. The method of claim 2 , further comprising:
determining that the second set of error control bits indicates that the data includes a multi-bit error that is uncorrectable, wherein transforming the second set of error control bits into the set of error control bits is based at least in part on the determining.
6. The method of claim 1 , further comprising:
transmitting, to the host device, a fourth signal comprising data retrieved from the memory device, the data associated with the set of error control bits, wherein transmitting the fourth signal is part of the transmitting the set of error control bits.
7. The method of claim 1 , wherein the set of error control bits comprises read link error correction code information associated with data transmitted to the host device from the memory device.
8. The method of claim 1 , wherein the request comprises a mode register read command.
9. A method at a host device, comprising:
receiving, from a memory device, a first signal comprising a set of error control bits indicating that an error log of the memory device comprises information for use by the host device;
transmitting, to the memory device in response to the first signal, a second signal comprising a request to retrieve the information of the error log; and
receiving, from the memory device in response to the second signal, a third signal comprising the information of the error log.
10. The method of claim 9 , further comprising:
refraining from using the set of error control bits for error correction or detection based at least in part on the set of error control bits indicating that the error log of the memory device comprises the information.
11. The method of claim 9 , further comprising:
receiving a fourth signal comprising a second set of error control bits; and
performing error detection, error correction, or both based at least in part on a value of the second set of error control bits differing from a value of the set of error control bits.
12. The method of claim 9 , further comprising:
receiving a fourth signal comprising a second set of error control bits; and
performing error detection, error correction, or both based at least in part on a polarity of at least one bit of the second set of error control bits differing from a polarity of at least one bit of the set of error control bits.
13. The method of claim 9 , further comprising:
receiving, from the memory device, a fourth signal comprising data associated with the set of error control bits indicating that the error log of the memory device comprises the information for use by the host device.
14. The method of claim 13 , wherein
the data comprises a second set of error control bits, and
the second set of error control bits indicates that the error log of the memory device comprises the information for use by the host device based at least in part on each bit of the second set of error control bits comprising a same value as each other bit of the second set of error control bits.
15. An apparatus, comprising:
a memory array comprising an array of memory cells that each comprise capacitive storage elements;
a circuit coupled with the memory array and configured to cause the apparatus to:
transmit, to a host device, a first signal comprising a set of error control bits indicating that an error log of the apparatus comprises information for use by the host device;
receive, from the host device in response to the first signal, a second signal comprising a request to retrieve the information of the error log; and
transmit, to the host device in response to the second signal, a third signal comprising the information of the error log.
16. The apparatus of claim 15 , wherein the circuit is configured to cause the apparatus to:
determine a second set of error control bits based at least in part on data retrieved from the apparatus; and
transforming the second set of error control bits into the set of error control bits based at least in part on the error log comprising the information, wherein transmitting the first signal that comprises the set of error control bits is based at least in part on transforming the second set of error control bits into the set of error control bits.
17. The apparatus of claim 16 , wherein the circuit is configured to cause the apparatus to:
determine that the error log includes the information for use by the host device, wherein transforming the second set of error control bits into the set of error control bits is based at least in part on the determining.
18. The apparatus of claim 16 , wherein the circuit is configured to cause the apparatus to:
determine that the second set of error control bits comprises an invalid error control code, wherein transforming the second set of error control bits into the set of error control bits is based at least in part on the determining.
19. The apparatus of claim 16 , wherein the circuit is configured to cause the apparatus to:
determine that the second set of error control bits indicates that the data includes a multi-bit error that is uncorrectable, wherein transforming the second set of error control bits into the set of error control bits is based at least in part on the determining.
20. The apparatus of claim 15 , wherein the circuit is configured to cause the apparatus to:
transmit, to the host device, a fourth signal comprising data retrieved from the apparatus, the data associated with the set of error control bits.
21. The apparatus of claim 15 , wherein the set of error control bits comprises read link error correction code information associated with data transmitted to the host device from the apparatus.
22. The apparatus of claim 15 , wherein the request comprises a mode register read command.
23. An apparatus, comprising:
a circuit configured to cause the apparatus to:
receive, from a memory device, a first signal comprising a set of error control bits indicating that an error log of the memory device comprises information for use by the apparatus;
transmit, to the memory device in response to the first signal, a second signal comprising a request to retrieve the information of the error log; and
receive, from the memory device in response to the second signal, a third signal comprising the information of the error log.
24. The apparatus of claim 23 , wherein the circuit is configured to cause the apparatus to:
refrain from using the set of error control bits for error correction or detection based at least in part on the set of error control bits indicating that the error log of the memory device comprises the information.
25. The apparatus of claim 23 , wherein the circuit is configured to cause the apparatus to:
receive a fourth signal comprising a second set of error control bits; and
perform error detection, error correction, or both based at least in part on a value of the second set of error control bits differing from a value of the set of error control bits.
26. The apparatus of claim 23 , wherein the circuit is configured to cause the apparatus to:
receive a fourth signal comprising a second set of error control bits; and
perform error detection, error correction, or both based at least in part on a polarity of at least one bit of the second set of error control bits differing from a polarity of at least one bit of the set of error control bits.
27. The apparatus of claim 23 , wherein the circuit is configured to cause the apparatus to:
receive, from the memory device, a fourth signal comprising data associated with the set of error control bits indicating that the error log of the memory device comprises the information for use by the apparatus.
28. The apparatus of claim 27 , wherein
the data comprises a second set of error control bits, and
the second set of error control bits indicates that the error log of the memory device comprises the information for use by the apparatus based at least in part on each bit of the second set of error control bits comprising a same value as each other bit of the second set of error control bits.