Techniques for indicating a write link error
Methods, systems, and devices for techniques for indicating a write link error are described. The method may include a memory device receiving, from a host device, a write command, data, and a first set of error control bits for the data. The memory device may determine that the data includes an uncorrectable error using the first set of error control bits and generate a second set of error control bits for the data based on determining that the data includes the uncorrectable error. Further, the method may include the memory device storing the data and the second set of error control bits in a memory device and transmitting, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based on the second set of error control bits.
1. A method by a memory system, comprising:
receiving a write command, data, and a first set of error control bits for the data;
determining, in response to receiving the write command, that the data includes an error based at least in part on the first set of error control bits;
generating a second set of error control bits for the data based at least in part on determining that the data includes the error, the second set of error control bits indicating that the data includes the error;
storing, in response to generating the second set of error control bits, the data and the second set of error control bits in the memory system; and
transmitting the data and an indication that the data includes the error based at least in part on a read command for the data.
2. The method of claim 1 , wherein transmitting the indication that the data includes the error comprises:
transmitting the second set of error control bits over a channel associated with communicating error control information.
3. The method of claim 1 , further comprising:
generating a single bit indicator flag based at least in part on the second set of error control bits, wherein the indication that the data includes the error comprises the single bit indicator flag.
4. The method of claim 1 , wherein transmitting the indication that the data includes the error comprises:
transmitting the indication that the data includes the error via a channel associated with communicating error control information, the channel different than a data channel.
5. The method of claim 1 , further comprising:
storing a bit at a register of a memory device of the memory system, wherein a logic value of the bit is based at least in part on determining that the data includes the error.
6. The method of claim 5 , further comprising:
reading the second set of error control bits stored in the memory device as part of a read operation performed on the data; and
reading the logic value of the bit stored at the register, wherein transmitting the indication that the data includes the error is based at least in part on the logic value.
7. The method of claim 1 , further comprising:
reading the data from a memory device as part of a read operation performed on the data; and
refraining from performing an error correction procedure on the data read from the memory device based at least in part on the second set of error control bits.
8. The method of claim 1 , wherein each bit of the second set of error control bits corresponds to a first logic value.
9. The method of claim 1 , wherein each bit of a first subset of the second set of error control bits corresponds to a first logic value and each bit of a second subset of the second set of error control bits corresponds to a second logic value, the second subset comprising one bit.
10. The method of claim 1 , wherein the first set of error control bits is for correcting errors associated with the data received from a host device over a link and the second set of error control bits is for correcting errors associated with reading data stored at a memory device or for correcting errors associated with data sent to the host device over the link.
11. The method of claim 1 , wherein the error comprises an uncorrectable error.
12. The method of claim 11 , wherein the uncorrectable error comprises a multi-bit error in the data.
13. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
receive a write command, data, and a first set of error control bits for the data;
determine, in response to receiving the write command, that the data includes an error based at least in part on the first set of error control bits;
generate a second set of error control bits for the data based at least in part on determining that the data includes the error, the second set of error control bits indicating that the data includes the error;
store, in response to generating the second set of error control bits, the data and the second set of error control bits; and
transmit the data and an indication that the data includes the error based at least in part on a read command for the data.
14. The non-transitory computer-readable medium of claim 13 , wherein the instructions to transmit the indication that the data includes the error are executable by the one or more processors to:
transmit the second set of error control bits over a channel associated with communicating error control information.
15. The non-transitory computer-readable medium of claim 13 , wherein the instructions are further executable by the one or more processors to:
generate a single bit indicator flag based at least in part on the second set of error control bits, wherein the indication that the data includes the error comprises the single bit indicator flag.
16. The non-transitory computer-readable medium of claim 13 , wherein the instructions to transmit the indication that the data includes the error are executable by the one or more processors to:
transmit the indication that the data includes the error via a channel associated with communicating error control information, the channel different than a data channel.
17. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive a write command, data, and a first set of error control bits for the data;
determine, in response to receiving the write command, that the data includes an error based at least in part on the first set of error control bits;
generate a second set of error control bits for the data based at least in part on determining that the data includes the error, the second set of error control bits indicating that the data includes the error;
store, in response to generating the second set of error control bits, the data and the second set of error control bits in the memory system; and
transmit the data and an indication that the data includes the error based at least in part on a read command for the data.
18. The memory system of claim 17 , wherein transmitting the indication that the data includes the error comprises the processing circuitry configured to cause the memory system to:
transmit the second set of error control bits over a channel associated with communicating error control information.
19. The memory system of claim 17 , wherein the processing circuitry is further configured to cause the memory system to:
generate a single bit indicator flag based at least in part on the second set of error control bits, wherein the indication that the data includes the error comprises the single bit indicator flag.