Semiconductor device and method of manufacturing the same
A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.
1. A semiconductor device, comprising:
a stack of parallel metal gates formed on a first side of a substrate;
a first pair of insulation regions extending across the stack of parallel metal gates;
a second pair of insulation regions replacing two of the parallel metal gates, wherein three or more metal gates are located between the second pair of insulation regions;
a first isolated region enclosed by the first and second pairs of insulation regions;
a first via formed within the first isolated region, wherein the first via extends through a portion of a center of the three metal gates within the first isolated region; and
an insulation layer replacing the three metal gates located within the first isolated region.
2. The semiconductor device according to claim 1 , wherein the first pair of insulation regions are made of materials selected from at least one of SiO, SiOC, AIO, AION, ZrO, HfO, TiO, ZrAIO, ZnO, SiOCN, SiOCN, and SiCN.
3. The semiconductor device according to claim 1 , wherein the second pair of insulation regions are made of at least one of SiCO, SiO, and SiOCN.
4. The semiconductor device according to claim 1 , wherein the first via extends beyond the middle of the three metal gates within the first isolated region in a direction along which the first pair of insulation region extends.
5. The semiconductor device according to claim 1 , wherein the first via is made of materials selected from at least one of W, Ru, Co, Cu, Ti, TIN, Ta, TaN, Mo, and Ni.
6. The semiconductor device according to claim 1 , wherein the first via has a top dimension of about 30 nm to about 100 nm and a bottom dimension of about 25 nm to about 90 nm.
7. The semiconductor device according to claim 1 , wherein the first via has a height of about 20 nm to about 100 nm.
8. The semiconductor device according to claim 1 , further comprising:
a third pair of insulation regions on a second side of the substrate, the second side being opposite to the first side and the third pair of insulation regions being aligned with the first pair of insulation regions;
a fourth pair of insulation regions on the second side of the substrate, the fourth pair of insulation regions being aligned with the second pair of insulation regions; and a second via within a second isolated region enclosed by the third and fourth pair of insulation regions, the second via being connected to the first via to form a feedthrough via.
9. The semiconductor device according to claim 8 , wherein the second via is made of materials selected from at least one of W, Ru, Co, Cu, Ti, TIN, Ta, TaN, Mo, and Ni.
10. The semiconductor device according to claim 8 , wherein the second via has a top dimension of about 30 nm to about 100 nm.
11. The semiconductor device according to claim 8 , wherein the second via has a bottom dimension of about 25 nm to about 90 nm.
12. The semiconductor according to claim 8 , wherein the second via has a height of about 20 nm to about 100 nm.
13. A semiconductor device, comprising:
a feedthrough via extending from a first side of a substrate to a second side of the substrate;
a first pair of insulation regions extending around the feedthrough via along a direction perpendicular to a stack of metal gates formed on the first side of the substrate;
a second pair of insulation regions formed by replacing two of the stack of metal gates, wherein the feedthrough via is formed between the second pair of insulation regions; and
a dielectric layer filling a space between the feedthrough via, the first pair of insulation regions, and second pair of insulation regions.
14. The semiconductor according to claim 13 , wherein the feedthrough via includes a frontside via formed at the first side of substrate connected with a backside via formed at the second side of the substrate.
15. A method of manufacturing a semiconductor device, comprising:
forming a field effective transistor (FET) device on a first side of a substrate;
defining a cell region isolated from other regions of the FET device;
removing metal gates located within the isolated cell region and refilling openings created by removing the metal gates with interlayer dielectric oxide material; and
forming a feedthrough via within the isolated cell region and extending through the substrate.
16. The method according to claim 15 , further comprising:
forming a first pair of insulation regions extending through a stack of the metal gates and a second pair of insulation region by removing two of the stack of metal gates and refilling with dielectric material to define the isolated cell region.
17. The method according to claim 15 , further comprising:
using a first CPODE mask for forming the second pair of insulation regions and a second CPODE mask for removing the metal gates within the isolated cell region.
18. The method according to claim 15 , wherein the isolated cell region includes at least three metal gates therewithin.
19. The method according to claim 15 , further comprising:
forming a plurality of source/drain contacts at both the first side and a second side of the substrate opposite to the first side, to contact with a plurality of source/drain regions formed on the first side of the substrate from both the first side and the second side of the substrate.
20. The method according to claim 15 , further comprising:
forming a frontside via extending through the isolated cell region and a backside via extending from the second side of the substrate to connect with the frontside via.