Gate-last tri-gate FeFET
View Patent ↗A semiconductor structure includes an isolation layer; first and second source/drain (S/D) metal electrodes over the isolation layer; a metal gate disposed laterally between the first and the second S/D metal electrodes; a ferroelectric layer on a bottom surface and sidewall surfaces of the metal gate; and an oxide semiconductor layer. The oxide semiconductor layer includes a first portion under the first and the second S/D metal electrodes; a second portion under the ferroelectric layer and being thicker than the first portion; third portions above the first and the second S/D metal electrodes, respectively; and fourth portions on sidewalls of the first and the second S/D metal electrodes, respectively, and connecting the third portions to the second portion.
1. A semiconductor structure, comprising:
an isolation layer;
first and second source/drain (S/D) metal electrodes over the isolation layer;
a metal gate disposed laterally between the first and the second S/D metal electrodes;
a ferroelectric layer on a bottom surface and sidewall surfaces of the metal gate; and
an oxide semiconductor layer, comprising:
a first portion under the first and the second S/D metal electrodes;
a second portion under the ferroelectric layer and being thicker than the first portion;
third portions above the first and the second S/D metal electrodes, respectively; and
fourth portions on sidewalls of the first and the second S/D metal electrodes, respectively, and connecting the third portions to the second portion.
2. The semiconductor structure of claim 1 , wherein each of the first and the second S/D metal electrodes includes Mo, Ti, Pd, W, Co, Cr, Cu, Ni, Ta, Pt, Au, Al, TiW, TiN, TaN, WN, or WCN.
3. The semiconductor structure of claim 1 , wherein the metal gate includes Mo, Ti, Pd, W, Co, Cr, Cu, Ni, Ta, Pt, Au, Al, TiW, TiN, TaN, WN, or WCN.
4. The semiconductor structure of claim 1 , wherein the ferroelectric layer includes Hf 1-x Zr x O 2 , BaMgF 4 , BaTiO 3 —PbZrO, (Ba,Sr)TiO 3 , Bi 4 Ti 3 O 12 , LiNbO 3 , LiTaO 3 , (Pb,La)TiO 3 , (Pb,La)(Zr,Ti)O 3 , Pb(Zr,Ti)O 3 , SrBi 2 Ta 2 O 9 , Bi 4-x La x Ti 3 O 12 , BiFeO 3 , YMnO 3 , YbMnO 3 , BiMnO 3 , Pb(Fe 0.5 W 0.5 ) 3 , or HfO 2 .
5. The semiconductor structure of claim 1 , wherein the oxide semiconductor layer includes amorphous indium tungsten oxide (a-IWO), amorphous indium zinc oxide (a-IZO), amorphous indium-tungsten-zinc oxide (a-IWZO), amorphous indium-tin-zinc oxide (a-ITZO), amorphous indium tin oxide (a-ITO), amorphous indium oxide (a-InO), SnO x , Cu x O, or NiO x .
6. The semiconductor structure of claim 1 , wherein the ferroelectric layer and the metal gate are disposed on top and sidewall surfaces of the second portion of the oxide semiconductor layer.
7. The semiconductor structure of claim 6 , wherein the second portion of the oxide semiconductor layer is in a shape of a square or a rectangle in a cross-sectional view cut perpendicular to a direction from the first S/D metal electrode to the second S/D metal electrode.
8. The semiconductor structure of claim 6 , wherein the second portion of the oxide semiconductor layer is in a shape of a semi-oval in a cross-sectional view cut perpendicular to a direction from the first S/D metal electrode to the second S/D metal electrode.
9. The semiconductor structure of claim 1 , further comprising:
a first via disposed on the first S/D metal electrode;
a second via disposed on the second S/D metal electrode;
a first metal line disposed on the first via and extending lengthwise along a first direction from the first S/D metal electrode to the second S/D metal electrode; and
a second metal line disposed on the second via and extending lengthwise along the first direction.
10. The semiconductor structure of claim 9 , wherein the first and the second S/D metal electrodes, the first and the second vias, and the first and the second metal lines include a same metal.
11. The semiconductor structure of claim 9 , wherein the first and the second S/D metal electrodes include a different metal than the first and the second vias and the first and the second metal lines.
12. The semiconductor structure of claim 1 , further comprising transistors below the isolation layer wherein the transistors are interconnected with the first and the second S/D metal electrodes and the metal gate.
13. A semiconductor structure, comprising:
an isolation layer;
first and second source/drain (S/D) metal electrodes over the isolation layer;
an oxide semiconductor layer, wherein a first portion of the oxide semiconductor layer is disposed between the first and the second S/D metal electrodes and connects the first and the second S/D metal electrodes;
a ferroelectric layer disposed on top and sidewall surfaces of the first portion of the oxide semiconductor layer; and
a metal gate disposed laterally between the first and the second S/D metal electrodes, on the ferroelectric layer, and on the top and sidewall surfaces of the first portion of the oxide semiconductor layer.
14. The semiconductor structure of claim 13 , wherein the oxide semiconductor layer further includes:
second portions on bottom surfaces of the first and the second S/D metal electrodes;
third portions on top surfaces of the first and the second S/D metal electrodes; and
fourth portions on sidewall surfaces of the first and the second S/D metal electrodes.
15. The semiconductor structure of claim 14 , wherein the first portion is thicker than each of the second portions, the third portions, and the fourth portions.
16. The semiconductor structure of claim 13 , further comprising:
first and second vias disposed on the first and the second S/D metal electrodes, respectively; and
first and second metal lines disposed on the first and the second vias, respectively.
17. The semiconductor structure of claim 16 , further comprising transistors below the isolation layer.
18. A method, comprising:
providing a stack of layers including an isolation layer, a first oxide semiconductor layer over the isolation layer, and a first metal layer over the first oxide semiconductor layer;
patterning the first metal layer to form source/drain metal electrodes;
depositing a second oxide semiconductor layer directly on the first oxide semiconductor layer and the source/drain metal electrodes;
patterning the first and the second oxide semiconductor layers to form oxide semiconductor channel layers;
depositing a ferroelectric layer on at least top and sidewall surfaces of the oxide semiconductor channel layers;
depositing a metal gate layer over the ferroelectric layer; and
performing a planarization process to the metal gate layer and the ferroelectric layer to expose the second oxide semiconductor layer.
19. The method of claim 18 , further comprising:
replacing portions of the metal gate layer with an isolation material.
20. The method of claim 19 , further comprising:
forming metal vias connecting to the source/drain metal electrodes; and
forming metal lines over and connecting to the metal vias.