Hybrid smart verify for QLC/TLC die
Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.
1. An apparatus comprising:
one or more control circuits configured to connect to a memory structure comprising non-volatile memory cells, wherein the one or more control circuits are configured to:
program a first group of the memory cells in the memory structure using a four-bit code having sixteen states and four pages;
program a second group of the memory cells in the memory structure using a three-bit code based on three pages of the four pages, wherein the three-bit code includes eight states of the sixteen states of the four-bit code for which an unused page of the four-bit code comprises a default value; and
begin to verify during programming using the three-bit code, for each particular state of a first set of one or more states of the eight states, during a program-verify loop determined based on whether a number of memory cells having a threshold voltage above a verify voltage for a state that immediately precedes the particular state in threshold voltage is greater than a pre-determined number.
2. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
begin to verify during programming using the three-bit code, for each particular state of a second set of one or more states of the eight states, during a program-verify loop determined based on a pre-determined number of program-verify loops following beginning to verify a state that immediately precedes the particular state in threshold voltage.
3. The apparatus of claim 2 , wherein:
the eight states includes an erase state, and A-, B-, C-, D-, E-, F-, and G-states in increasing threshold voltages; and
the first set includes the B-state.
4. The apparatus of claim 3 , wherein:
the second set includes the C-, D-, E-, F-, and G-states.
5. The apparatus of claim 2 , wherein the first set comprises:
all states in the three-bit code that immediately follow a state in the four-bit code that is also used in the three-bit code.
6. The apparatus of claim 5 , wherein:
the eight states includes an erase state, and A-, B-, C-, D-, E-, -F, and G-states in increasing threshold voltages; and
the first set includes the B-state whether the B-state follows a state in the four-bit code that is also used in the three-bit code or whether the B-state follows a state in the four-bit code that is not used in the three-bit code.
7. The apparatus of claim 5 , wherein the second set comprises:
states in the three-bit code that immediately follow a state in the four-bit code that is not used in the three-bit code, but does not include any state in the four-bit code that is also used in the three-bit code.
8. The apparatus of claim 1 wherein to program the second group of the memory cells in the memory structure using the three-bit code based on three of the four pages of the four-bit code includes the one or more control circuits being further configured to:
load three data pages into a corresponding three sets of data latches associated with memory cells; and
load the default value into a fourth set of data latches associated with memory cells, wherein the default value is the same for all data latches in the fourth set of data latches.
9. The apparatus of claim 8 , wherein the one or more control circuits are further configured to:
program the three data pages into the memory cells based on a programming algorithm that considers the three data pages in the corresponding three sets of data latches and the default value in the fourth set of data latches.