IP Library › Granted Patent US 12,626,761
Granted Patent B2
US 12,626,761 · App. 17/897,460 · Granted May 12, 2026

Memory circuitry and method used in forming memory circuitry

Inventors: John D. Hopkins (Meridian, ID); Alyssa N. Scarbrough (Boise, ID)
Assignee: Micron Technology, Inc.
G11C16/0483H10B41/10H10B41/27H10B41/35H10B43/10H10B43/27H10B43/35
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Quick Facts
Patent No.
US 12,626,761
App. No.
17/897,460
Granted
May 12, 2026
Kind
B2
Abstract

Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs extending along a first direction. Multiple different-depth and height-sequential treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The cavity comprises a pair of laterally-opposing outermost sidewalls relative to the second direction and that individually extend along the first direction. The multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls. Methods are disclosed.

Claims (34)

1 . A method used in forming memory circuitry, comprising:

forming a stack comprising vertically-alternating first tiers and second tiers, the stack extending from a memory-array region into a stair-step region, the stair-step region comprising a cavity comprising a flight of stairs extending along a first direction, the first tiers being conductive and the second tiers being insulative at least in a finished-circuitry construction, the cavity comprising a pair of laterally-opposing outermost sidewalls relative to a second direction that is orthogonal to the first direction and that individually extend along the first direction;

forming a series of first and second spacers in the cavity, the first and second spacers extending along the first direction directly above the flight of stairs, the first spacers having a different composition than the second spacers, the series of spacers having first spacers alternating with second spacers along the second direction;

forming masking material directly above the series of first and second spacers, the masking material comprising an opening there-through that exposes a single spacer of the first and second spacers, the single spacer being laterally-closest to one of the laterally-opposing outermost sidewalls, the masking material covering all remaining of the first and second spacers; and

using the masking material in a plurality of alternating etching and lateral-trimming steps that progressively widen the opening and form multiple different-depth treads in individual of the stairs along the second direction, each of the lateral-trimming steps individually exposing a single next-in-series spacer comprised by the series of first and second spacers through the masking material and covering all then-remaining, if any, of the first and second spacers with the masking material, the etching steps individually removing only one of the alternating first and second spacers as a result of the respective lateral-trimming step followed by etching through one of the first tiers and one of the second tiers that was there-below, individual of the treads comprising conducting material of individual of the first tiers in the finished-circuitry construction.

2 . The method of claim 1 wherein forming at least some of the series of first and second spacers comprises:

forming a spacer-forming layer above and within the cavity; and

anisotropically etching the spacer-forming layer above and within the cavity.

3 . The method of claim 2 wherein less-than-all of the spacers are formed by anisotropically etching the respective spacer-forming layer within the cavity.

4 . The method of claim 3 wherein a majority of the collective first and second spacers is formed by the anisotropically etching of the respective spacer-forming layer within the cavity.

5 . The method of claim 1 wherein the masking material comprises photoresist.

6 . The method of claim 1 wherein each of the different compositions is different from those of the first and second tiers.

7 . The method of claim 1 wherein one of the different compositions is carbon.

8 . The method of claim 1 wherein one of the different compositions is polysilicon.

9 . The method of claim 1 wherein one of the different compositions is carbon and the other of the different compositions is polysilicon.

10 . The method of claim 1 wherein total number of the alternating first and second spacers in the cavity is five.

11 . The method of claim 1 wherein the individual stairs have total number of the multiple different-depth treads in the finished-circuitry construction that is five.

12 . The method of claim 1 wherein,

total number of the alternating first and second spacers in the series is five; and

the individual stairs have total number of the multiple different-depth treads in the finished-circuitry construction that is five.

13 . The method of claim 1 wherein the multiple different-depth treads in the finished-circuitry construction are height-sequential along the second direction in the individual stairs.

14 . The method of claim 13 wherein the multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls.

15 . The method of claim 14 wherein the individual stairs have total number of the multiple different-depth treads in the finished-circuitry construction that is five.

16 . The method of claim 1 wherein the first and second spacers are of the same lateral-width in the second direction.

17 . A method used in forming memory circuitry, comprising:

forming a stack comprising vertically-alternating first tiers and second tiers, the stack extending from a memory-array region into a stair-step region, the stair-step region comprising a cavity comprising a flight of stairs extending along a first direction, the first tiers being conductive and the second tiers being insulative at least in a finished-circuitry construction, the cavity comprising a pair of laterally-opposing outermost sidewalls relative to a second direction that is orthogonal to the first direction and that individually extend along the first direction;

forming fill material in the cavity directly above the flight of stairs;

forming masking material directly above the fill material, the masking material comprising an opening there-through that exposes a portion of the fill material that is laterally-closest to one of the laterally-opposing outermost sidewalls and extends there-along in the first direction, the masking material covering all remaining of the fill material but for the portion; and

using the masking material in a plurality of alternating etching and lateral-trimming steps that progressively widen the opening from the laterally-closest sidewall along the first direction and form multiple different-depth treads in individual of the stairs along the second direction, the lateral-trimming steps individually exposing a next-in-succession portion of the fill material that extends along the first direction and covering all then-remaining, if any, of the fill material, the etching steps individually removing the respective next-in-succession portion as a result of the respective lateral-trimming step followed by etching through one of the first tiers and one of the second tiers that was there-below, individual of the treads comprising conducting material of individual of the first tiers in the finished-circuitry construction.

18 . The method of claim 17 wherein the masking material comprises photoresist.

19 . The method of claim 17 wherein the individual stairs have total number of the multiple different-depth treads that is five.

20 . The method of claim 17 wherein the multiple different-depth treads in in the finished-circuitry construction are height-sequential along the second direction in the individual stairs.

21 . The method of claim 20 wherein the multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls.

22 . The method of claim 21 wherein the individual stairs have total number of the multiple different-depth treads in the finished-circuitry construction that is five.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: HOPKINS, JOHN D.; SCARBROUGH, ALYSSA N.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 060925/0268 →
Continuity (1)
Related Publication 20240071496A1 · Feb 29, 2024
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