IP Library Granted Patent US 11,935,944
Granted Patent B2
US 11,935,944 · App. 17/902,224 · Granted Mar 19, 2024

Semiconductor device and method for fabricating the same

Inventors: Shunpei Yamazaki (Tokyo, JP); Hideomi Suzawa (Kanagawa, JP); Shinya Sasagawa (Kanagawa, JP); Motomu Kurata (Kanagawa, JP); Masashi Tsubuku (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/66969H01L21/02565H01L27/1225H01L27/127H01L27/14616H01L27/14689H01L29/7869H01L29/78696
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Quick Facts
Patent No.
US 11,935,944
App. No.
17/902,224
Granted
Mar 19, 2024
Kind
B2
Abstract

The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

Claims (24)

1. A semiconductor device comprising:

a plurality of circuits:

the plurality of circuits each comprising:

a first transistor comprising a channel formation region comprising an oxide semiconductor;

a second transistor comprising a channel formation region comprising silicon; and

a capacitor,

wherein a source or a drain of the first transistor is electrically connected to a gate of the second transistor, and

wherein the gate of the second transistor is electrically connected to the capacitor,

a first conductive layer;

an oxide semiconductor layer comprising a region over the first conductive layer;

a first insulating layer comprising a region over the oxide semiconductor layer;

a second conductive layer comprising a region over the first insulating layer; and

a second insulating layer comprising a region over the second conductive layer,

wherein the first conductive layer comprises a region functioning as one of a source electrode and a drain electrode of the first transistor,

wherein the oxide semiconductor layer comprises a region configured to function as the channel formation region of the first transistor,

wherein the first insulating layer comprises a region configured to function as a gate insulating layer of the first transistor,

wherein the second conductive layer comprises a region configured to function as a gate electrode of the first transistor,

wherein the oxide semiconductor layer is in contact with part of a top surface and a side surface of the first conductive layer,

wherein in a cross-sectional view of the first transistor along a channel length direction, the first insulating layer comprises an extended region extending beyond an end portion of the second conductive layer,

wherein the second insulating layer is an oxide insulating layer, and

wherein the second insulating layer comprises a region in contact with the top surface of the extended region of the first insulating layer, a region in contact with a side surface of the first insulating layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with the top surface of the first conductive layer.

2. The semiconductor device according to claim 1 , wherein in the cross-sectional view of the first transistor along the channel length direction, a length of the extended region of the first insulating layer is smaller than 3 μm.

3. The semiconductor device according to claim 1 , wherein in the cross-sectional view of the first transistor along the channel length direction, a side surface of the first conductive layer overlapping with the oxide semiconductor layer comprises a stepped shape.

4. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2022
From: YAMAZAKI, SHUNPEI; SUZAWA, HIDEOMI; SASAGAWA, SHINYA; KURATA, MOTOMU; TSUBUKU, MASASHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 060979/0529 →
Priority Claims (1)
JP 2012-203385 · Sep 14, 2012 · national
Continuity (6)
Continuation 17167332 · Feb 4, 2021
Continuation 16671612 · Nov 1, 2019
Continuation 16194444 · Nov 19, 2018
Division 15461575 · Mar 17, 2017
Division 14021618 · Sep 9, 2013
Related Publication 20220416061A1 · Dec 29, 2022