IP Library Granted Patent US 12,706,330
Granted Patent B2
US 12,706,330 · App. 17/906,443 · Granted Aug 11, 2026

Power storage device and electronic device

Inventors: Kei Takahashi (Isehara, JP); Kazuki Tanemura (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01M10/46H01M10/4264H02J7/70
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Quick Facts
Patent No.
US 12,706,330
App. No.
17/906,443
Filed
Sep 15, 2022
Granted
Aug 11, 2026
Kind
B2
Art Unit
2859
USPC
320/107
Abstract

A power storage device or the like with low power consumption is provided. Alternatively, a power storage device or the like with high integration is provided. A first battery cell includes a first electrode over a first substrate, a positive electrode active material layer over the first electrode, an electrolyte layer over the positive electrode active material layer, a negative electrode active material layer over the electrolyte layer, and a second electrode over the negative electrode active material layer. The comparison circuit includes a first input terminal, a second input terminal, an output terminal, and a first transistor. The first transistor includes an oxide semiconductor over the first substrate, a first insulator over the oxide semiconductor, and a gate electrode over the first insulator. The first electrode is electrically connected to the gate of the first transistor and the first input terminal. The comparison circuit has a function of outputting a first signal in response to a result of comparison between a potential of the first electrode and a desired reference potential from the output terminal to the control circuit. The control circuit has a function of controlling charging of the first battery cell in accordance with the first signal.

Claims (53)

1 . A power storage device comprising a first substrate, a first battery cell, a comparison circuit, and a control circuit,

wherein the comparison circuit comprises a first input terminal, a second input terminal, an output terminal, and a first transistor,

wherein the first transistor comprises an oxide semiconductor over the first substrate, a first insulator over the oxide semiconductor, and a gate electrode over the first insulator,

wherein a second insulator is provided over the gate electrode of the first transistor,

wherein the first battery cell comprises a first electrode over the second insulator, a positive electrode active material layer over the first electrode, an electrolyte layer over the positive electrode active material layer, a negative electrode active material layer over the electrolyte layer, and a second electrode over the negative electrode active material layer,

wherein the first electrode is electrically connected to the gate electrode of the first transistor and the first input terminal,

wherein a third electrode is provided over the second insulator and electrically connected to one of a source electrode and a drain electrode of the first transistor,

wherein the first electrode and the third electrode comprise a same material,

wherein the comparison circuit is configured to output a first signal in response to a result of comparison between a potential of the first electrode and a desired reference potential from the output terminal to the control circuit, and

wherein the control circuit is configured to control charging of the first battery cell in accordance with the first signal.

2 . The power storage device according to claim 1 , further comprising a second transistor and a capacitor,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the second input terminal and one electrode of the capacitor, and

wherein the second transistor comprises an oxide semiconductor.

3 . The power storage device according to claim 1 , wherein the output terminal is electrically connected to the one of the source electrode and the drain electrode of the first transistor.

4 . The power storage device according to claim 1 , further comprising a second transistor comprising an oxide semiconductor, a third transistor comprising an oxide semiconductor, and a capacitor,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the second input terminal, a gate electrode of the third transistor, and one electrode of the capacitor, and

wherein the output terminal is electrically connected to one of a source electrode and a drain electrode of the third transistor.

5 . The power storage device according to claim 1 ,

wherein the first electrode and the third electrode each comprise a titanium compound.

6 . The power storage device according to claim 1 ,

wherein the first electrode, the source electrode of the first transistor, and the drain electrode of the first transistor each comprise a titanium compound.

7 . The power storage device according to claim 1 , wherein the first electrode and the gate electrode of the first transistor each comprise a titanium compound.

8 . The power storage device according to claim 1 , further comprising a second battery cell, a converter circuit, a clock generation circuit, a booster circuit, and a voltage retention circuit,

wherein the first transistor comprises a back gate electrode,

wherein the converter circuit is configured to convert a positive electrode potential of the second battery cell and supply the potential as a second signal to the clock generation circuit,

wherein the clock generation circuit is configured to generate a third signal as a clock signal, with use of the second signal,

wherein the booster circuit is configured to generate a first potential with use of the third signal, and

wherein the voltage retention circuit is configured to supply the first potential to the back gate electrode to be retained.

9 . The power storage device according to claim 1 , wherein the first substrate is any of a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, a semiconductor substrate, an SOI substrate, and a plastic substrate.

10 . The power storage device according to claim 1 ,

wherein the first substrate is a semiconductor substrate,

wherein the first substrate comprises silicon, and

wherein a transistor with a channel formation region in the first substrate is included.

11 . A power storage device comprising:

a first substrate;

a first transistor comprising an oxide semiconductor over the first substrate, a first insulator over the oxide semiconductor, and a gate electrode over the first insulator;

a second insulator over the oxide semiconductor;

a first battery cell comprising a first electrode over the second insulator, a positive electrode active material layer over the first electrode, an electrolyte layer over the positive electrode active material layer, a negative electrode active material layer over the electrolyte layer, and a second electrode over the negative electrode active material layer;

a third electrode over the second insulator; and

a fourth electrode overlapping the third electrode with a third insulator provided therebetween,

wherein the first electrode and the fourth electrode comprise a same material, and

wherein the third electrode is electrically connected to one of a source electrode and a drain electrode of the first transistor.

12 . The power storage device according to claim 11 , wherein the first electrode and the third electrode comprise a titanium compound.

13 . The power storage device according to claim 11 , wherein the first transistor comprises the oxide semiconductor in a channel formation region.

14 . The power storage device according to claim 11 ,

wherein the first electrode and the fourth electrode each comprise a titanium compound.

15 . The power storage device according to claim 11 , further comprising:

a fifth electrode over the second insulator; and

a piezoelectric layer overlapping with the fifth electrode,

wherein the first electrode and the fifth electrode each comprise a titanium compound.

16 . An electronic device comprising a display portion, a driver circuit, and the power storage device according to claim 1 ,

wherein the driver circuit is configured to supply an image signal to the display portion, and

wherein the driver circuit comprises a plurality of transistors comprising an oxide semiconductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2023
From: TAKAHASHI, KEI; TANEMURA, KAZUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 062355/0962 →
Priority Claims (1)
JP 2020-057843 · Mar 27, 2020 · national
Continuity (1)
Related Publication 20230144022A1 · May 11, 2023
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