Backside contact that reduces risk of contact to gate short
Embodiments of the invention include a transistor comprising a gate region and an epitaxial region, the transistor comprising a frontside opposite a backside. A backside contact is coupled to the epitaxial region and separated from the gate region by a bottom dielectric isolation layer and a backside protective spacer.
1 . A semiconductor structure comprising:
a transistor comprising a gate region, an inner spacer material forming inner spacers adjacent to channel regions, and an epitaxial region, the transistor comprising a frontside opposite a backside; and
a backside contact coupled to the epitaxial region and separated from the gate region by a bottom dielectric isolation layer and a backside protective spacer, wherein the bottom dielectric isolation layer and the backside protective spacer are in contact with the backside contact and are positioned below the inner spacers, wherein the inner spacers are on a first side of the bottom dielectric isolation layer and the backside protective spacer is on a second side of the bottom dielectric isolation layer, the second side being opposite the first side;
wherein the backside protective spacer is substantially a width and a material of an inner spacer.
2 . The semiconductor structure of claim 1 , wherein the bottom dielectric isolation layer extends a length of the channel regions.
3 . The semiconductor structure of claim 1 , wherein an inner spacer is formed between channel regions of the transistor.
4 . The semiconductor structure of claim 1 , wherein the backside contact forms an inverted T shape, with a transition region adjacent to the backside protective spacer.
5 . The semiconductor structure of claim 1 , wherein a front side contact is coupled to another epitaxial region of the transistor.
6 . The semiconductor structure of claim 1 , wherein the backside contact is on the backside of the transistor and a front side contact is on the front side.
7 . The semiconductor structure of claim 1 , wherein the backside protective spacer comprises an insulator material.
8 . The semiconductor structure of claim 1 , wherein the backside protective spacer and the bottom dielectric isolation layer comprise different materials.
9 . The semiconductor structure of claim 1 , wherein the backside protective spacer is adjacent to the bottom dielectric isolation layer.
10 . A method comprising:
forming a transistor comprising a gate region, an inner spacer material forming inner spacers adjacent to channel regions, and an epitaxial region, the transistor comprising a frontside opposite a backside; and
providing a backside contact coupled to the epitaxial region and separated from the gate region by a bottom dielectric isolation layer and a backside protective spacer, wherein the bottom dielectric isolation layer and the backside protective spacer are in contact with the backside contact and are positioned below the inner spacers, wherein the inner spacers are on a first side of the bottom dielectric isolation layer and the backside protective spacer is on a second side of the bottom dielectric isolation layer, the second side being opposite the first side;
wherein the backside protective spacer is substantially a width and a material of an inner spacer.
11 . The method of claim 10 , wherein the backside protective spacer is formed under the bottom dielectric isolation layer, substantially aligned with an inner spacer.
12 . The method of claim 10 , wherein an inner spacer is formed between channel regions of the transistor.
13 . The method of claim 10 , wherein the backside contact forms an inverted T shape, with a transition region adjacent to the backside protective spacer.
14 . The method of claim 10 , wherein a front side contact is coupled to another epitaxial region of the transistor.
15 . The method of claim 10 , wherein the backside contact is on the backside of the transistor and a front side contact is on the front side.
16 . The method of claim 10 , wherein the backside protective spacer comprises an insulator material.
17 . The method of claim 10 , wherein the backside protective spacer and the bottom dielectric isolation layer comprise different materials.
18 . The method of claim 10 , wherein the backside protective spacer is adjacent to the bottom dielectric isolation layer.