Contact resistance reduction in transistor devices with metallization on both sides
Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.
1. A transistor device, comprising:
a stack of semiconductor channels;
a first source/drain region on a first end of the semiconductor channels;
a second source/drain region on a second end of the semiconductor channels, wherein the first source/drain region and the second source/drain region have a top surface and a bottom surface;
a first source/drain contact electrically coupled to the top surface of the first source/drain region;
a second source/drain contact electrically coupled to the bottom surface of the second source/drain region, wherein a top surface of the second source/drain contact is separated from the second source/drain region by an interfacial layer, the interfacial layer comprising a single material layer continuous along the top surface and side surfaces of the second source/drain contact, and wherein the interfacial layer is a semiconductor material.
2. The transistor device of claim 1 , wherein the interfacial layer has an active dopant concentration of approximately 4E20 cm −3 or greater.
3. The transistor device of claim 2 , wherein the interfacial layer comprises silicon or silicon and carbon, and wherein a dopant comprises one or both of phosphorous and arsenic.
4. The transistor device of claim 1 , wherein a thickness of the interfacial layer is less than 15 nm.
5. The transistor device of claim 1 , further comprising:
an isolation layer over the bottom surface of the second source/drain region, wherein the second source/drain contact passes through the isolation layer.
6. The transistor device of claim 5 , wherein the interfacial layer separates the second source/drain contact from the isolation layer through an entire thickness of the isolation layer.
7. The transistor device of claim 5 , wherein the interfacial layer separates the second source/drain contact from the isolation layer through a portion of a thickness of the isolation layer.
8. The transistor device of claim 1 , wherein the bottom surface of the second source/drain region comprises a trench.
9. The transistor device of claim 8 , wherein the interfacial layer lines the trench, and wherein the second source/drain contact fills the trench.
10. The transistor device of claim 1 , wherein the second source/drain contact comprise a stack of different conductive materials.
11. The transistor device of claim 1 , wherein the stack of semiconductor channels comprises a stack of nanowire or nanoribbon channels.
12. The transistor device of claim 1 , wherein the second source/drain contact comprises a first width and a second width that is smaller than the first width.
13. The transistor device of claim 1 , wherein the second source/drain contact extends into the second source/drain region.
14. An electronic system, comprising:
a board;
an electronic package attached to the board; and
a die electrically coupled to the electronic package, wherein the die comprises:
a nanowire or nanoribbon transistor, comprising:
a stack of semiconductor channels;
a gate stack over the semiconductor channels;
source/drain regions on opposite ends of the semiconductor channels;
a first contact to a top surface of a first one of the source/drain regions; and
a second contact to a bottom surface of a second one of the source/drain regions, wherein a top surface of the second source/drain contact is separated from the second one of the source/drain regions by an interfacial layer, the interfacial layer comprising a single material layer continuous along the top surface and side surfaces of the second source/drain contact, and wherein the interfacial layer is a semiconductor material.
15. The electronic system of claim 14 , further comprising:
an isolation layer beneath the bottom surface of the second one of the source/drain regions, wherein a hole is disposed through the isolation layer, and wherein the interfacial layer lines the hole.
16. The electronic system of claim 14 , wherein the second source/drain contact extends into the second one of the source/drain regions.