System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects
Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array.
1. An imaging sensor comprising:
a pixel array comprising a plurality of pixels formed into a plurality of pixel columns, wherein the plurality of pixel columns are divided into a plurality of pixel sub-columns;
a plurality of pixel sub-column buses that correspond with the plurality of pixel sub-columns, such that at least one of the plurality of pixel sub-column buses is associated with one of the plurality of pixel sub-columns such that each of the plurality of pixel sub-columns are configured to be read independently;
a plurality of supporting circuits configured to process data received from the plurality of pixels, wherein the plurality of supporting circuits are formed into a plurality of supporting circuit columns, and wherein the plurality of supporting circuit columns are divided into a plurality of supporting circuit sub-columns;
a plurality of supporting circuit sub-column buses that correspond with the plurality of supporting circuit sub-columns, such that at least one of the plurality of supporting circuit sub-column buses is associated with one of the plurality of supporting circuit sub-columns;
wherein at least a portion of the plurality of supporting circuit sub-column buses and at least a portion of the plurality of pixel sub-columns buses are superimposed; and
a plurality of interconnects, wherein at least one interconnect electrically connects each of the plurality of pixel sub-column buses to each of the plurality of supporting circuit sub-column buses such that each of the plurality of supporting circuit sub-columns receives pixel data from a corresponding pixel sub-column;
wherein the plurality of interconnects are positioned anywhere along an intercept of the plurality of pixel sub-column buses and the plurality of circuit sub-column buses, wherein the intercept is defined by the superimposition of the at least a portion of the plurality of pixel sub-column buses directly with the at least a portion of the plurality of the circuit sub-column buses.
2. The imaging sensor of claim 1 , wherein each pixel sub-column bus and each supporting circuit sub-column bus are superimposed, such that at least a portion of each pixel sub-column bus and at least a portion of each supporting circuit sub-column bus overlap; and
wherein at least one of the plurality of interconnects provides an electrical connection between each pixel sub-column bus and each supporting circuit sub-column bus at the overlap.
3. The imaging sensor of claim 2 , wherein the electrical connection between one pixel sub-column and one supporting circuit sub-column bus is accomplished by a single interconnect.
4. The imaging sensor of claim 2 , wherein the electrical connection between one pixel sub-column bus and one supporting circuit sub-column bus is accomplished by a plurality of interconnects.
5. The imaging sensor of claim 1 , wherein said imaging sensor is backside illuminated.
6. The imaging sensor of claim 1 , wherein the imaging sensor comprises a plurality of substrates;
wherein the plurality of substrates comprise a first substrate that comprises the plurality of pixel sub-columns, and a second substrate that is disposed remotely relative to the first substrate that comprises the plurality of supporting circuit sub-columns;
wherein the interconnect that provides the electrical connection is disposed between the first substrate and the second substrate.
7. The imaging sensor of claim 6 , wherein one of the plurality of supporting circuit sub-columns corresponds with and is dedicated to one of the plurality of pixel sub-columns of the pixel array.
8. The imaging sensor of claim 1 , wherein a portion of the plurality of pixel sub-columns are electrically connected to a corresponding portion of the plurality of supporting circuit sub-columns that are supporting the pixel column in which the portion of the plurality of pixel sub-columns reside.
9. The imaging sensor of claim 1 , wherein each pixel sub-column is electronically isolated from other pixel sub-columns.
10. The imaging sensor of claim 1 , wherein each of the plurality of pixel sub-columns are electrically configured to be read at substantially the same time to a corresponding supporting circuit sub-column.
11. A method of accessing data comprising:
electronically connecting a pixel array to supporting circuits of an imaging sensor;
wherein the pixel array comprises a plurality of pixels formed into a plurality of pixel columns, wherein the plurality of pixel columns are divided into a plurality of pixel sub-columns;
wherein the imaging sensor comprises a plurality of pixel sub-column buses that correspond with the plurality of pixel sub-columns, such that at least one of the plurality of pixel sub-column buses is associated with one of the plurality of pixel sub-columns such that each of the plurality of pixel sub-columns are configured to be read independently;
wherein the imaging sensor comprises a plurality of supporting circuits configured to process data received from the plurality of pixels, wherein the plurality of supporting circuits are formed into a plurality of supporting circuit columns, and wherein the plurality of supporting circuit columns are divided into a plurality of supporting circuit sub-columns;
wherein the imaging sensor comprises a plurality of supporting circuit sub-column buses that correspond with the plurality of supporting circuit sub-columns, such that at least one of the plurality of supporting circuit sub-column buses is associated with one of the plurality of supporting circuit sub-columns;
reading data out from the plurality of pixel sub-columns starting with a first pixel in each of the plurality of sub-columns and sequentially reading out data from each of the pixels in the pixel sub-column until the last pixel in the sub-column is read;
transmitting the data from each of the plurality of pixel sub-column buses through at least one interconnect to a corresponding supporting circuit sub-column bus;
processing the data into a visual frame for display;
wherein at least a portion of the plurality of supporting circuit sub-column buses and at least a portion of the plurality of pixel sub-columns buses are superimposed;
wherein the at least one interconnect is positioned anywhere along an intercept of the plurality of pixel sub-column buses and the plurality of circuit sub-column buses, wherein the intercept is defined by the superimposition of the at least a portion of the plurality of pixel sub-column buses directly with the at least a portion of the plurality of the circuit sub-column buses.
12. The method of accessing data of claim 11 , further comprising reading data from each pixel sub-column simultaneously.
13. The method of accessing data of claim 11 , further comprising transmitting data from one of the plurality of pixel sub-columns to a corresponding one of the plurality of supporting circuit sub-columns, wherein data is simultaneously transmitted from the plurality of pixel sub-columns from within the same pixel column.
14. The method of accessing data of claim 11 , wherein the plurality of supporting circuit sub-columns receive data or signals via the interconnects located between pixel sub-column buses and corresponding supporting circuit sub-column buses, wherein the data or signals from one pixel sub-column is processed by one supporting circuit sub-column.
15. The method of accessing data of claim 11 , wherein reading pixel sub-columns within the same pixel column simultaneously comprises: reading and processing data, by supporting circuits within a specific supporting circuit sub-column, in parallel within supporting circuits located in different supporting circuit sub-column within the same circuit column.
16. The method of accessing data of claim 11 , wherein each pixel sub-column bus and each supporting circuit sub-column bus are superimposed, such that at least a portion of each pixel sub-column bus and at least a portion of each supporting circuit sub-column bus overlap; and
wherein at least one of the plurality of interconnects provides an electrical connection between each pixel sub-column bus and each supporting circuit sub-column bus at the overlap.
17. The method of accessing data of claim 16 , wherein the imaging sensor is backside illuminated.
18. The method of accessing data of claim 11 , wherein the imaging sensor comprises a plurality of substrates;
wherein the plurality of substrates comprise a first substrate that comprises the plurality of pixel sub-columns, and a second substrate that is disposed remotely relative to the first substrate that comprises the plurality of supporting circuit sub-columns;
wherein the interconnect that provides the electrical connection is disposed between the first substrate and the second substrate.
19. The method of accessing data of claim 18 , wherein one of the plurality of supporting circuit sub-columns corresponds with and is dedicated to one of the plurality of pixel sub-columns of the pixel array.
20. The method of accessing data of claim 11 , wherein each pixel sub-column is electronically isolated from other pixel sub-columns.