IP Library Granted Patent US 12,652,759
Granted Patent B2
US 12,652,759 · App. 17/931,651 · Granted Jun 9, 2026

Leadframe mounting with lead insertion for lead wall bonding

Inventors: Chad Chen (Suzhou, CN); Jiahui Liu (Suzhou, CN); Wuxing Xia (Suzhou, CN); Jingyan Liu (Suzhou, CN)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H05K1/18H05K3/3485H05K3/3494H10W70/429H05K3/3426H05K2201/10757H05K2201/10863H05K2201/10878H05K2201/10946
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Quick Facts
Patent No.
US 12,652,759
App. No.
17/931,651
Granted
Jun 9, 2026
Kind
B2
Abstract

A semiconductor device package may include a substrate having an insulating layer with a patterned conductive layer formed thereon, the patterned conductive layer including at least a first pattern portion and a second pattern portion. The semiconductor device package may include a leadframe having a lead that is soldered to the substrate with solder provided in an opening between the first pattern portion and the second pattern portion and with the lead inserted into the opening.

Claims (46)

1 . A method of making a semiconductor device package, comprising:

patterning a patterned conductive layer on an insulating layer of a substrate, the patterned conductive layer including at least a first pattern portion and a second pattern portion;

applying solder paste within an opening between the first pattern portion and the second pattern portion and at least partially on the insulating layer;

positioning a leadframe on the patterned conductive layer;

inserting a lead of the leadframe within the solder paste; and

heating the solder paste to solder bond the lead to the first pattern portion and the second pattern portion on the substrate with the lead inserted into the opening.

2 . The method of claim 1 , wherein the patterning of the patterned conductive layer on the insulating layer comprises patterning the first pattern portion and the second pattern portion separated from one another on the insulating layer with the opening formed as a groove between the first pattern portion and the second pattern portion.

3 . The method of claim 1 , wherein the patterning of the patterned conductive layer on the insulating layer comprises patterning the first pattern portion and the second pattern portion connected to one another on the insulating layer with the opening formed as a hole between the first pattern portion and the second pattern portion.

4 . The method of claim 1 , wherein the heating the solder paste comprises:

performing a vacuum reflow process.

5 . The method of claim 1 , further comprising:

positioning at least one semiconductor device on the lead; and

encapsulating the at least one semiconductor device, the lead, and the substrate with a molding material.

6 . A method of making a semiconductor device package, comprising:

forming a substrate having an insulating layer with a patterned conductive layer formed thereon, the patterned conductive layer including at least a first pattern portion and a second pattern portion; and

providing a leadframe on the patterned conductive layer with a lead that is soldered to the first pattern portion and the second pattern portion on the substrate with solder provided at least partially on the insulating layer in an opening between the first pattern portion and the second pattern portion and with the lead inserted into the opening.

7 . The method of claim 6 , further comprising:

inserting an end portion of the lead into the opening and positioned between a surface of the patterned conductive layer and a surface of the insulating layer.

8 . The method of claim 6 , further comprising:

forming the solder at least partially on a surface of the insulating layer within the opening.

9 . The method of claim 6 , wherein the first pattern portion and the second pattern portion are separated from one another on the insulating layer, the opening is a groove formed between the first pattern portion and the second pattern portion, and further comprising:

bonding an end portion of the lead by the solder to walls of the groove.

10 . The method of claim 6 , wherein the first pattern portion and the second pattern portion are connected to one another on the insulating layer, the opening is a hole formed within the patterned conductive layer, and further comprising:

bonding an end portion of the lead by the solder to walls of the hole.

11 . The method of claim 6 , further comprising:

forming the patterned conductive layer on a first side of the insulating layer; and

forming a conductive layer on an opposed second side of the insulating layer.

12 . The method of claim 11 , wherein the substrate is a direct bonded metal (DBM) substrate, in which the patterned conductive layer and the conductive layer are formed using copper and the insulating layer is formed using a ceramic material.

13 . The method of claim 6 , wherein the lead includes a lead post and a lead body, and further comprising:

inserting the lead post into the opening and bonded to the first pattern portion and the second pattern portion using the solder; and

forming the lead body at an angle to the lead post.

14 . The method of claim 6 , further comprising:

forming the lead with a Z-shape having a first portion formed at a first angle to a second portion, and a third portion formed at a second angle with the second portion; and

at least partially inserting the third portion into the opening and bonded to the first pattern portion and the second pattern portion using the solder.

15 . A method of making a semiconductor device package, comprising:

forming a substrate having an insulating layer with a patterned conductive layer formed thereon, the patterned conductive layer including at least a first pattern portion and a second pattern portion; and

forming a leadframe positioned on the patterned conductive layer and having a lead with a lead end portion that is inserted into an opening between the first pattern portion and the second pattern portion, and that is soldered to at least one wall of the opening and to the insulating layer.

16 . The method of claim 15 , wherein the first pattern portion and the second pattern portion are separated from one another on the insulating layer, and the opening is a groove formed between the first pattern portion and the second pattern portion.

17 . The method of claim 15 , wherein the first pattern portion and the second pattern portion are connected to one another on the insulating layer, and the opening is a hole formed within the patterned conductive layer.

18 . The method of claim 15 , further comprising:

forming the lead end portion at an angle to a lead body of the lead.

19 . The method of claim 15 , further comprising:

providing the lead with a Z-shape having a first portion formed at a first angle to a second portion, and with the lead end portion formed at a second angle with the second portion.

20 . The method of claim 15 , further comprising:

forming the patterned conductive layer on a first side of the insulating layer; and

forming a conductive layer on an opposed second side of the insulating layer.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 061879, FRAME 0655 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064123/0001 →
SECURITY INTEREST Recorded Nov 3, 2022
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 061879/0655 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2022
From: CHEN, CHAD; LIU, JIAHUI; XIA, WUXING; LIU, JINGYAN
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 061076/0570 →
Continuity (1)
Related Publication 20240090130A1 · Mar 14, 2024
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