Temperature detection using negative temperature coefficient resistor in GaN setting
A structure includes a negative temperature coefficient (NTC) resistor for use in gallium nitride (GaN) technology. The NTC resistor includes a p-type doped GaN (pGaN) layer, and a gallium nitride (GaN) heterojunction structure under the pGaN layer. The GaN heterojunction structure includes a barrier layer and a channel layer. An isolation region extends across an interface of the barrier layer and the channel layer, and a first metal electrode is on the pGaN layer spaced from a second metal electrode on the pGaN layer. The NTC resistor can be used as a temperature compensated reference in a structure providing a temperature detection circuit. The temperature detection circuit includes an enhancement mode HEMT sharing parts with the NTC resistor and includes temperature independent current sources including depletion mode HEMTs.
1. A structure, comprising:
a negative temperature coefficient (NTC) resistor including:
a p-type doped gallium nitride (pGaN) layer;
a gallium nitride (GaN) heterojunction structure under the pGaN layer, the GaN heterojunction structure including a barrier layer and a channel layer;
an isolation region extending across an interface of the barrier layer and the channel layer; and
a first metal electrode on the pGaN layer spaced from a second metal electrode on the pGaN layer.
2. The structure of claim 1 , wherein the barrier layer includes aluminum gallium nitride (AlGaN) having an aluminum (Al) mole fraction between 15-25%.
3. The structure of claim 1 , wherein the pGaN layer and the first and second metal electrodes are adjacent a high electron mobility transistor (HEMT).
4. The structure of claim 3 , wherein the first metal electrode and the pGaN layer form part of a gate of the HEMT structure.
5. The structure of claim 1 , wherein the isolation region includes an amorphizing dopant species including at least one of argon and nitrogen.
6. The structure of claim 1 , wherein the isolation region is directly under the pGaN layer.
7. The structure of claim 1 , wherein the barrier layer includes a portion directly under the pGaN layer, and the isolation region surrounds the portion of the barrier layer.
8. The structure of claim 1 , wherein the NTC resistor is part of a temperature detection circuit including:
a first temperature independent current source;
a second temperature independent current source;
an enhancement mode high electron mobility transistor (EM HEMT) having a gate, a first source/drain region and a second source/drain region;
a first node coupling the first temperature independent current source, the first metal electrode of the NTC resistor and the gate of the EM HEMT;
a second node coupling the first source/drain region of the EM HEMT and the second metal electrode of the NTC resistor to ground; and
an output node coupling the second source/drain region of the EM HEMT and the second temperature independent current source,
wherein in response to a temperature crossing a threshold, a voltage change at the NTC resistor and at the gate of EM HEMT causes the EM HEMT to change states.
9. The structure of claim 8 , wherein the first temperature independent current source and the second temperature independent current source each include a depletion mode HEMT (DM HEMT) having a gate, a first source/drain region and a second source/drain region, and a zero-temperature coefficient (ZTC) resistor coupled between the first source/drain region and the gate of the DM HEMT, wherein the second source/drain region of the DM HEMT is coupled to a voltage source.
10. The structure of claim 9 , wherein the ZTC resistor includes a silicon-chromium resistor.
11. A structure, comprising:
a first temperature independent current source;
a second temperature independent current source;
an enhancement mode high electron mobility transistor (EM HEMT) having a gate, a first source/drain region and a second source/drain region;
a negative temperature coefficient (NTC) resistor including a first metal electrode and a second metal electrode;
a first node coupling the first temperature independent current source, the first metal electrode of the NTC resistor and the gate of the EM HEMT;
a second node coupling the first source/drain region of the EM HEMT and the second metal electrode of the NTC resistor to ground; and
an output node coupling the second source/drain region of the EM HEMT and the second temperature independent current source.
12. The structure of claim 11 , wherein in response to a temperature crossing a threshold, a voltage change at the NTC resistor and at the gate of EM HEMT causes the EM HEMT to change states.
13. The structure of claim 11 , wherein the first temperature independent current source and the second temperature independent current source each include a depletion mode HEMT (DM HEMT) having a gate, a first source/drain region and a second source/drain region, and a zero-temperature coefficient (ZTC) resistor coupled between the first source/drain region and the gate of the DM HEMT, wherein the second source/drain region of the DM HEMT is coupled to a voltage source.
14. The structure of claim 11 , wherein the NTC resistor includes:
a p-type doped gallium nitride (pGaN) layer;
a gallium nitride (GaN) heterojunction structure under the pGaN layer, the GaN heterojunction structure including a barrier layer and a channel layer;
an isolation region extending across an interface of the barrier layer and the channel layer; and
at least two spaced-apart metallic electrodes on the pGaN layer.
15. The structure of claim 14 , wherein the pGaN layer, the barrier layer, and the channel layer are shared with the EM HEMT.
16. The structure of claim 14 , wherein the barrier layer includes aluminum gallium nitride (AlGaN) having an aluminum (Al) mole fraction between 15-25%.
17. The structure of claim 14 , wherein the isolation region includes an amorphizing dopant species including at least one of argon and nitrogen.
18. The structure of claim 14 , wherein the isolation region is directly under the pGaN layer.
19. The structure of claim 14 , wherein the barrier layer includes a portion directly under the pGaN layer, and the isolation region surrounds the portion of the barrier layer.
20. A structure, comprising:
a first temperature independent current source and a second temperature independent current source, wherein the first temperature independent current source and the second temperature independent current source each include a depletion mode HEMT (DM HEMT) having a gate, a first source/drain region and a second source/drain region, and a zero-temperature coefficient (ZTC) resistor coupled between the first source/drain region and the gate of the DM HEMT, wherein the second source/drain region of the DM HEMT is coupled to a voltage source;
an enhancement mode high electron mobility transistor (EM HEMT) having a gate, a first source/drain region and a second source/drain region;
a negative temperature coefficient (NTC) resistor including a first metal electrode and a second metal electrode;
a first node coupling the first temperature independent current source, the first metal electrode of the NTC resistor and the gate of the EM HEMT;
a second node coupling the first source/drain region of the EM HEMT and the second metal electrode of the NTC resistor to ground; and
an output node coupling the second source/drain region of the EM HEMT and the second temperature independent current source,
wherein in response to a temperature crossing a threshold, a voltage change at the NTC resistor and at the gate of EM HEMT causes the EM HEMT to change states.
21. A negative temperature coefficient (NTC) resistor, comprising:
a p-type doped gallium nitride (pGaN) layer;
a gallium nitride (GaN) heterojunction structure under the pGaN layer, the GaN heterojunction structure including a barrier layer and a channel layer;
an isolation region extending across an interface of the barrier layer and the channel layer; and
a first metal electrode on the pGaN layer spaced from a second metal electrode on the pGaN layer.