Power semiconductor device with integrated temperature protection

1. A temperature protected power semiconductor device comprising a substrate, the substrate comprising:

a power field effect transistor comprising a gate electrode connected to a gate, a drift region, and a first terminal and a second terminal for a load current, wherein the load current is controllable during operation by a voltage applied between the gate and the first terminal; and

a thermosensitive element comprising first, second and third doped regions formed in the substrate, wherein the first doped region forms a p-n junction with the second doped region, wherein the second doped region forms a p-n junction with the third doped region, wherein the first doped region is directly conductively connected with the gate electrode, and wherein the third doped region is directly conductively connected with the first terminal,

wherein the thermosensitive element is thermally coupled to the power field effect transistor,

wherein the thermosensitive element is configured to cause the power field effect transistor to reduce the load current in case of an exceedance of a limit temperature of the power field effect transistor by interconnecting the gate and the first terminal via conduction across the first, second and third doped regions of the thermosensitive element.

2. The temperature protected power semiconductor device of claim 1 , wherein the thermosensitive element is a bipolar transistor having an emitter, a collector, and a base, wherein the first doped region is the collector, wherein the second doped region is the base, and wherein the third doped region is the emitter, and wherein the base is electrically open.

3. The temperature protected power semiconductor device of claim 2 , wherein the bipolar transistor is configured such that, above the limit temperature, the voltage between the gate and the first terminal is pulled below a threshold voltage of the power field effect transistor.

4. The temperature protected power semiconductor device of claim 2 , wherein the bipolar transistor is disposed in a trench in a surface of the substrate.

5. The temperature protected power semiconductor device of claim 4 , wherein the surface of the substrate and a surface of the trench are covered with a first isolation layer.

6. The temperature protected power semiconductor device of claim 2 , wherein the bipolar transistor is disposed adjacent to a surface of the substrate.

7. The temperature protected power semiconductor device of claim 6 , wherein the bipolar transistor is isolated from the substrate by an isolation layer.

8. The temperature protected power semiconductor device of claim 2 , wherein the bipolar transistor comprises one of: a horizontally oriented stack having at least one p-doped layer and at least one n-doped layer; and a vertically oriented stack having at least one p-doped layer and at least one n-doped layer.

9. The temperature protected power semiconductor device of claim 1 , wherein a plurality of regularly distributed trenches are formed in the substrate.

10. The temperature protected power semiconductor device of claim 2 , wherein a plurality of elongated trenches with bipolar transistors are formed in parallel in the substrate.

11. The temperature protected power semiconductor device of claim 1 , wherein the power field effect transistor is one of: a FET; a Power MOSFET; and an IGBT.

12. The temperature protected power semiconductor device of claim 2 , wherein the power semiconductor device is a vertical device, wherein the substrate comprises a front surface and a back surface, and wherein the bipolar transistor is provided adjacent to the front surface.

13. The temperature protected power semiconductor device of claim 1 , wherein the first, second and third doped regions each extend to an upper surface of the substrate.

14. A method for producing a temperature protected power semiconductor device, the method comprising:

providing a substrate;

forming, in the substrate, a power field effect transistor comprising a gate electrode connected to a gate, a drift region, and a first terminal and a second terminal for a load current; and

forming a thermosensitive element having a negative temperature coefficient and comprising first, second and third doped regions formed in the substrate, wherein the first doped region forms a p-n junction with the second doped region, wherein the second doped region forms a p-n junction with the third doped region, wherein the first doped region is directly conductively connected with the gate electrode, and wherein the third doped region is directly conductively connected with the first terminal

wherein the thermosensitive element is thermally coupled to the power field effect transistor,

wherein the thermosensitive element is configured to cause the power field effect transistor to reduce the load current in case of an exceedance of a limit temperature of the power field effect transistor by interconnecting the gate and the first terminal via conduction across the first, second and third doped regions of the thermosensitive element.

15. The method of claim 14 , wherein the thermosensitive element is a bipolar transistor comprising an emitter, a collector, and a base, wherein the first doped region is the collector, wherein the second doped region is the base, and wherein the third doped region is the emitter wherein the base is electrically open, wherein the bipolar transistor is thermally connected to the power field effect transistor.

16. The method of claim 14 , wherein the power field effect transistor is a vertical device disposed between a front surface of the substrate and a back surface of the substrate, and wherein the method further comprises:

forming a trench in the front surface of the substrate; and

forming the thermosensitive element in the trench.

17. The method of claim 15 , further comprising: forming an isolation layer on a front surface of the substrate; and forming the bipolar transistor on the isolation layer.

18. The method of claim 14 , wherein the first, second and third doped regions each extend to an upper surface of the substrate.