Switching-cycle voltage deviation control for modular multilevel converters
Aspects of switching-cycle voltage deviation control for modular multilevel converters (MMCs) are described. In one example, an upper switching action of an upper power cell is determined within a time duration of a switching cycle for an MMC. In addition, a lower switching action of a lower power cell is determined within the time duration of the switching cycle for the MMC. In addition, a delay is generated between the upper switching action and the lower switching action to reduce capacitor voltage deviation between the upper power cell and the lower power cell during the switching cycle. The upper power cell is located in an upper arm of a phase leg of the MMC, while the lower power cell is located in a lower arm of the phase leg of the MMC.
1 . A method for control of a modular multilevel converter (MMC), comprising:
determining, by a controller device, an upper switching action of an upper power cell in an upper arm of a phase leg of the MMC within a time duration of a switching cycle for the MMC;
determining, by the controller device, a lower switching action of a lower power cell in a lower arm of the phase leg of the MMC within the time duration of the switching cycle for the MMC;
solving, by the controller device, equality constraints within the time duration of the switching cycle to obtain a derived circulating current for the upper arm and the lower arm, the equality constraints comprising capacitor voltage changes for at least one capacitor in the upper arm and capacitor voltage changes for at least one capacitor in the lower arm; and
generating, by the controller device, a delay between the upper switching action and the lower switching action based on the derived circulating current obtained from solving the equality constraints to reduce capacitor voltage deviation between the upper power cell and the lower power cell during the switching cycle.
2 . The method of claim 1 , wherein solving the equality constraints sets a voltage change of a capacitor of at least one of the upper power cell and the lower power cell to be zero during the time duration of the switching cycle.
3 . The method of claim 2 , wherein the voltage change of the capacitor is based on an average circulating current through the upper arm and the lower arm during the time duration of the switching cycle, a capacitance of the capacitor, a type of switching action of the at least one of the upper power cell and the lower power cell, and an output current of the phase leg.
4 . The method of claim 1 , wherein obtaining the derived circulating current comprises determining, by the controller device, a derived circulating current pattern for upper power cells in the upper arm of the phase leg and for lower power cells in the lower arm of the phase leg over the switching cycle of the MMC based on solving the equality constraints.
5 . The method of claim 4 , wherein the derived circulating current pattern comprises a derived circulating current for each time duration among a plurality of time durations within the switching cycle of the MMC.
6 . The method of claim 1 , wherein the upper switching action comprises a switch of the upper power cell from a high level to a low level or from a low level to a high level.
7 . The method of claim 6 , wherein the high level comprises a positive capacitor connection of the upper power cell and the low level comprises a bypass connection or a negative capacitor connection of the upper power cell.
8 . The method of claim 1 , wherein the delay is regulated based on a reduced small signal modeling (RSSM) control method.
9 . The method of claim 1 , wherein the upper switching action comprises a nearest-level pulse width modulation switching action or a carrier phase-shift based modulation switching action.
10 . The method of claim 1 , wherein the upper power cell comprises a capacitor and a switch network.
11 . A modular multilevel converter (MMC), comprising:
a phase leg comprising an upper arm and a lower arm, the upper arm comprising an upper power cell and the lower arm comprising a lower power cell; and
a controller configured to:
determine an upper switching action of the upper power cell within a time duration of a switching cycle for the MMC;
determine a lower switching action of the lower power cell within the time duration of the switching cycle for the MMC;
solve equality constraints within the time duration of the switching cycle to obtain a derived circulating current for the upper arm and the lower arm, the equality constraints comprising capacitor voltage changes for at least one capacitor in the upper arm and capacitor voltage changes for at least one capacitor in the lower arm; and
generate a delay between the upper switching action and the lower switching action based on the derived circulating current obtained from solving the equality constraints to reduce capacitor voltage deviation between the upper power cell and the lower power cell during the switching cycle.
12 . The MMC of claim 11 , wherein, to solve the equality constraints, the controller is further configured to set a voltage change of a capacitor of at least one of the upper power cell and the lower power cell to be zero during the time duration of the switching cycle.
13 . The MMC of claim 12 , wherein the voltage change of the capacitor is based on an average circulating current through the upper arm and the lower arm during the time duration of the switching cycle, a capacitance of the capacitor, a type of switching action of the at least one of the upper power cell and the lower power cell, and an output current of the phase leg.
14 . The MMC of claim 11 , wherein the controller, in being configured to obtain the derived circulating current, is configured to determine a derived circulating current pattern for upper power cells in the upper arm of the phase leg and for lower power cells in the lower arm of the phase leg over the switching cycle of the MMC based on solving the equality constraints.
15 . The MMC of claim 14 , wherein the derived circulating current pattern comprises a derived circulating current for each time duration among a plurality of time durations within the switching cycle of the MMC.
16 . The MMC of claim 11 , wherein the lower switching action comprises a switch of the lower power cell from a low level to a high level or from a high level to a low level.
17 . The MMC of claim 16 , wherein the high level comprises a positive capacitor connection of the lower power cell and the low level comprises a bypass connection or a negative capacitor connection of the lower power cell.
18 . The MMC of claim 11 , wherein the lower power cell comprises a switch network.