INTEGRATED CIRCUIT (IC) DEVICE WITH HYBRID METAL LAYER
An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.
1 . An integrated circuit (IC) device, comprising:
a first structure comprising a first metal;
a second structure comprising a second metal, wherein the second metal is different from the first metal;
a third structure wrapping around at least part of the second structure; and
a fourth structure over the second structure in a first direction,
wherein the third structure and the fourth structure comprise an electrically conductive material, a height of the second structure in the first direction is greater than a height of the first structure in the first direction, and a width of the second structure in a second direction orthogonal to the first direction is greater than a height of the first structure in the second direction.
2 . The IC device according to claim 1 , wherein the width of the first structure is not greater than about 12 nanometers, or the width of the second structure is between about 20 and 50 nanometers.
3 . The IC device according to claim 1 , wherein a height of the fourth structure in the first direction is at least 3 nanometers.
4 . The IC device according to claim 1 , wherein:
the second structure comprises a first cross-section and a second cross-section,
the fourth structure is closer to the first cross-section than the second cross-section, and
a width of the first cross-section along the second direction is greater than a width of a width of the second cross-section.
5 . The IC device according to claim 1 , wherein:
the second structure comprises a first cross-section and a second cross-section,
the fourth structure is closer to the first cross-section than the second cross-section, and
a width of the first cross-section along the second direction is greater than a width of a width of the second cross-section.
6 . The IC device according to claim 1 , further comprising:
a fifth structure comprising a third metal;
a first via between the first structure and the fifth structure; and
a second via between the second structure and the fifth structure,
wherein a height of the first via in the first direction is greater than a height of the second via in the first direction.
7 . The IC device according to claim 6 , wherein the third metal is the same as the second metal.
8 . The IC device according to claim 1 , wherein the first structure is coupled to a source region or a drain region of a transistor, and the second structure is coupled to a channel region of the transistor.
9 . The IC device according to claim 1 , wherein the first metal is ruthenium, or the second metal is copper.
10 . The IC device according to claim 1 , wherein the electrically conductive material comprises cobalt.
11 . An integrated circuit (IC) device, comprising:
a transistor comprising a source region, a drain region, and a channel region;
a first layer comprising a first structure and a second structure, wherein the first structure is coupled to the source region or the drain region, the second structure is coupled to the channel region, a width of the first structure in a first direction is smaller than a width of the second structure in the first direction; and
a second layer comprising a third metal,
wherein a distance between the first structure and the second layer in a second direction orthogonal to the first direction is longer than a distance between the second structure and the second layer in the second direction.
12 . The IC device according to claim 11 , wherein the first layer is between the transistor and the second layer in the second direction.
13 . The IC device according to claim 11 , wherein the first structure is at least part of a wordline of a memory device, and the second structure is at least part of a bitline of the memory device.
14 . The IC device according to claim 11 , further comprising.
a first via between the first structure and the second layer; and
a second via between the second structure and the second layer,
wherein a length of the first layer in the second direction is greater than a length of the second layer in the second direction.
15 . The IC device according to claim 11 , wherein the first structure, the second structure, and the second layer are separated by one or more electrical insulators.
16 . A method for forming an integrated circuit (IC) device, the method comprising:
forming a first structure in a first opening in a structure, wherein the first structure comprises a first metal, and the structure comprises an electrical insulator;
forming a layer, wherein at least part of the layer is in a second opening and over one or more surfaces of the second opening, the layer comprises a first electrically conductive material, the layer forms a new opening, and a width of the first opening is smaller than a width of the second opening;
forming a second structure in the new opening, wherein the second structure comprises a second metal and is at least partially wrapped by the layer; and
forming a third structure over the second structure, wherein the third structure comprises a second electrically conductive material.
17 . The method according to claim 16 , further comprising:
before forming the third structure over the second structure, removing a portion of the layer or a portion of the second structure.
18 . The method according to claim 16 , further comprising:
after forming the third structure over the second structure, providing an electrical insulator over the third structure;
forming openings in the electrical insulator, wherein the openings have different dimensions; and
forming vias in the openings, wherein the vias comprise a first via connected to the first structure and a second via connected to the third structure.
19 . The method according to claim 18 , wherein forming openings in the electrical insulator comprises:
forming the openings through a selective etching process, wherein a rate of etching the electrical insulator is higher than a rate of etching the second electrically conductive material in the selective etching process.
20 . The method according to claim 16 , wherein the width of the first opening is not greater than 12 nanometers, and the width of the second opening is in a range from 20 to 50 nanometers.