Apparatus, semiconductor device, and redistribution layer structure thereof
According to one or more embodiments of the disclosure, an apparatus comprising a metal layer and a redistribution layer on the metal layer is provided. The redistribution layer includes an insulating layer, a via, and a redistribution metal layer. The via is in the insulating layer and has a rectangular shape in a plan view. The redistribution metal layer has a first thickness on a shorter side of the rectangular shape of the via and a second thickness on a longer side of the rectangular shape of the via. The second thickness is greater than the first thickness.
1. An apparatus, comprising:
a metal layer; and
a redistribution layer on the metal layer, the redistribution layer comprising:
an insulating layer;
a via in the insulating layer, the via having a rectangular shape in a plan view; and
a redistribution metal layer having a first thickness on a shorter side of the rectangular shape of the via and a second thickness on a longer side of the rectangular shape of the via, the second thickness greater than the first thickness.
2. The apparatus according to claim 1 , wherein
the first thickness and the second thickness are on the shorter side and the longer side of the rectangular shape in a lower portion of the via, respectively, and
the redistribution metal layer further has a third thickness on the shorter side of the rectangular shape in an upper portion of the via, the third thickness greater than the first thickness.
3. The apparatus according to claim 1 , wherein an aspect ratio between a height of the via and a shorter-side length of the via is equal to or greater than 1.0.
4. The apparatus according to claim 1 , wherein
the metal layer includes a plurality of metal wirings,
the apparatus further comprises an air gap between neighboring metal wirings among the plurality of metal wirings, and
a top part of the air gap is higher than an upper surface of each of the neighboring metal wirings.
5. The apparatus according to claim 4 , wherein the air gap is not exposed on an upper surface of the insulating layer of the redistribution layer.
6. The apparatus according to claim 1 , where the metal layer is a top metal layer of a plurality of metal layers.
7. The apparatus according to claim 1 , wherein the apparatus is a memory device.
8. A semiconductor device, comprising:
a metal layer on a semiconductor substrate; and
a redistribution layer on the metal layer, the redistribution layer comprising:
an insulating layer;
a via in the insulating layer, the via extending through the insulating layer and reaching the metal layer; and
a redistribution metal layer at least on an inner sidewall of the via and an upper surface of the insulating layer, wherein
the via has a rectangular shape in a plan view, providing a via opening shorter in a first horizontal direction and longer in a second horizontal direction over the metal layer, and
the redistribution metal layer on the inner sidewall of the via has a first thickness on a shorter side of the rectangular shape of the via and a second thickness on a longer side of the rectangular shape of the via, the second thickness greater than the first thickness.
9. The semiconductor device according to claim 8 , wherein an aspect ratio between a height of the via and a shorter-side length of the via is equal to or greater than 1.0.
10. The semiconductor device according to claim 8 , wherein
the first thickness and the second thickness are on the shorter side and the longer side of the rectangular shape in a lower portion of the via, respectively, and
the redistribution metal layer further has a third thickness on the shorter side of the rectangular shape in an upper portion of the via, the third thickness greater than the first thickness.
11. The semiconductor device according to claim 8 , wherein the redistribution metal layer includes aluminum.
12. The semiconductor device according to claim 8 , wherein
the metal layer includes a plurality of metal wirings, and
the semiconductor device further comprises an air gap between neighboring metal wirings among the plurality of metal wirings.
13. The semiconductor device according to claim 12 , wherein a top part of the air gap is higher than an upper surface of each of the neighboring metal wirings.
14. The semiconductor device according to claim 12 , wherein the air gap is not exposed on an upper surface of the insulating layer of the redistribution layer.
15. The semiconductor device according to claim 8 , where the metal layer is a top metal layer of a plurality of metal layers on the semiconductor substrate.
16. A redistribution layer structure, comprising:
an insulating layer;
a via in the insulating layer, the via extending through the insulating layer in a vertical direction; and
a redistribution metal layer on an inner sidewall of the via and an upper surface of the insulating layer, wherein
the via has a rectangular shape in a plan view, providing a via opening shorter in a first horizontal direction and longer in a second horizontal direction,
the redistribution metal layer includes a side portion on the inner sidewall of the via, and
the side portion of the redistribution metal layer has a first thickness on a shorter side of the rectangular shape of the via and a second thickness on a longer side of the rectangular shape of the via, the second thickness greater than the first thickness.
17. The redistribution layer structure according to claim 16 , wherein
the first thickness and the second thickness are on the shorter side and the longer side of the rectangular shape in a lower portion of the via, respectively, and
the side portion of the redistribution metal layer further has a third thickness on the shorter side of the rectangular shape in an upper portion of the via, the third thickness greater than the first thickness.
18. The redistribution layer structure according to claim 16 , wherein an aspect ratio between a height of the via and a shorter-side length of the via is equal to or greater than 1.0.
19. The redistribution layer structure according to claim 16 , wherein
the insulating layer is on a metal layer, and
the metal layer is on a semiconductor substrate.