IP Library Granted Patent US 12,550,708
Granted Patent B2
US 12,550,708 · App. 17/651,820 · Granted Feb 10, 2026

Top via interconnect with an embedded antifuse

Inventors: Kenneth Chun Kuen Cheng (Shatin, HK); Koichi Motoyama (Clifton Park, NY); Chanro Park (Clifton Park, NY); Chih-Chao Yang (Glenmont, NY)
Assignee: International Business Machines Corporation
H01L23/5226H01L23/5252H01L23/5283
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Quick Facts
Patent No.
US 12,550,708
App. No.
17/651,820
Granted
Feb 10, 2026
Kind
B2
Abstract

An antifuse structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line, and a conductive etch stop layer separating both the first metal line and the second metal line from an underlying layer, where a first portion of the conductive etch stop layer directly beneath the first metal line comprises a first extension region and a second portion of the conductive etch stop layer directly beneath the second metal line comprises a second extension region opposite the first extension region.

Claims (21)

1 . An antifuse structure comprising:

a first metal line comprising a length greater than a uniform width;

a top via above and directly contacting the first metal line;

a second metal line parallel to the first metal line and comprising a length greater than a uniform width; and

a conductive etch stop layer separating both the first metal line and the second metal line from an underlying layer, wherein a thickness of the conductive etch stop layer is less than a thickness of each of the first metal line and the second metal line, wherein a first portion of the conductive etch stop layer directly beneath the first metal line comprises a first extension region and a second portion of the conductive etch stop layer directly beneath the second metal line comprises a second extension region opposite the first extension region, and wherein the first portion of the conductive etch stop layer is completely separated from the second portion of the conductive etch stop layer by an interlevel dielectric layer.

2 . The antifuse structure according to claim 1 , wherein a distance between the first extension region and the second extension region is approximately 50 percent of a distance between the first metal line and the second metal line.

3 . The antifuse structure according to claim 1 , wherein the first metal line and the second metal line are directly on top of and cover completely the conductive etch stop layer except for the first extension region and the second extension region such that top surfaces of the first extension region and the second extension region directly contact an interlevel dielectric layer.

4 . The antifuse structure according to claim 1 , wherein the first extension region extends perpendicular to the length of the first metal line in a direction towards the second metal line and the second extension region extends perpendicular to the length of the second metal line in a direction towards the first metal line.

5 . The antifuse structure according to claim 1 , wherein the first extension region and the second extension region are aligned with the top via in a direction parallel to the length of the first metal line.

6 . The antifuse structure according to claim 1 , wherein the first extension region and the second extension region are laterally offset from the top via in a direction parallel to the length of the first metal line.

7 . An antifuse structure comprising: a first metal line; a top via above and directly contacting the first metal line, wherein the first metal line and the top via consist of a homogenous conductive material without an interface, wherein a width of the top via is substantially equal to a width of the first metal line; a second metal line adjacent and parallel to the first metal line; and a conductive etch stop layer separating both the first metal line and the second metal line from an underlying layer, wherein a first portion of the conductive etch stop layer directly beneath the first metal line comprises a first extension region and a second portion of the conductive etch stop layer directly beneath the second metal line comprises a second extension region opposite the first extension region.

8 . The antifuse structure according to claim 7 , wherein a distance between the first extension region and the second extension region is less than a distance between the first metal line and the second metal line.

9 . The antifuse structure according to claim 7 , wherein the first metal line and the second metal line are directly on top of and cover completely the conductive etch stop layer except for the first extension region and the second extension region such that top surfaces of the first extension region and the second extension region directly contact an interlevel dielectric layer.

10 . The antifuse structure according to claim 7 , wherein the first extension region extends perpendicular to a length of the first metal line in a direction towards the second metal line and the second extension region extends perpendicular to a length of the second metal line in a direction towards the first metal line.

11 . The antifuse structure according to claim 7 , wherein the first extension region and the second extension region are aligned with the top via in a direction parallel to a length of the first metal line.

12 . The antifuse structure according to claim 7 , wherein the first extension region and the second extension region are laterally offset from the top via in a direction parallel to a length of the first metal line.

13 . An antifuse structure comprising: a first conductive etch stop layer comprising a first extension region; a first metal line directly on top of and completely covering all of the first conductive etch stop layer except for the first extension region such that a top surface of the first extension region directly contacts an interlevel dielectric layer; a top via above and directly contacting the first metal line, wherein a width of the top via is substantially equal to a width of the first metal line; a second conductive etch stop layer comprising a second extension region aligned with the first extension region; and a second metal line directly on top of and completely covering all of the second conductive etch stop layer except for the second extension region such that a top surface of the second extension region directly contacts the interlevel dielectric layer.

14 . The antifuse structure according to claim 13 , wherein the first metal line and the top via consist of a homogenous conductive material.

15 . The antifuse structure according to claim 13 , wherein the first extension region extends in a direction towards the second metal line and the second extension region extends in a direction towards the first metal line.

16 . The antifuse structure according to claim 13 , wherein the first extension region and the second extension region are aligned with the top via.

17 . The antifuse structure according to claim 13 , wherein the first extension region and the second extension region are laterally offset from the top via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2022
From: CHENG, KENNETH CHUN KUEN; MOTOYAMA, KOICHI; PARK, CHANRO; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 059055/0423 →
Continuity (1)
Related Publication 20230268267A1 · Aug 24, 2023
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