BEOL anti-fuse structures for gate last semiconductor devices
An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.
1. A method comprising:
initiating a programming current in an anti-fuse structure configured to prevent an operating current from flowing between a first electrode and a second electrode in a non-programmed state of the anti-fuse structure, the programming current being configured to flow in a substantially axial plane between the first electrode and a portion of the second electrode, the first electrode and the portion of the second electrode being concentrically separated by a dielectric material; and
terminating the programming current after sufficient breakdown of the dielectric material,
wherein sufficient breakdown of the dielectric material enables the operating current to flow between the first electrode and the second electrode in a programmed state of the anti-fuse structure.
2. The method according to claim 1 , comprising initiating the programming current for 5 to 50 microseconds.
3. The method according to claim 1 , wherein the programming current is 2 to 20 milliamperes.
4. The method according to claim 1 , wherein the programming current establishes a voltage of 1 to 2 volts between the first and second electrodes.
5. The method according to claim 1 , wherein the first electrode is concentrically formed about the first portion of the second electrode, and the first electrode has a ring or oval shape.
6. The method according to claim 5 , wherein a distance between the first portion of the second electrode and the first electrode is 40 nm.
7. The method of claim 1 , wherein the first electrode and the portion of the second electrode are formed as part of a first metallization layer of a semiconductor device, and a second portion of the second electrode is formed as part of a second metallization layer of the semiconductor device, the anti-fuse structure including at least one via electrically connecting the first and second portions of the second electrode.
8. The method according to claim 7 , wherein:
the first metallization layer is a metal 1 layer; and
the dielectric material comprises SiCOH having a dielectric constant of 2.7.
9. The method according to claim 7 , wherein:
the first metallization layer is one of a metal 2 layer through a metal 8 layer; and
the dielectric material comprises an ultra low-k (ULK) material having a dielectric constant of 2.55.