IP Library › Granted Patent US 12,562,703
Granted Patent B2
US 12,562,703 · App. 17/937,892 · Granted Feb 24, 2026

Offset correction circuit

Inventor: Tomokazu Kojima (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H03F3/45771H03F3/345H03F3/45183H03F3/72H03F3/45475H03F2203/45212H03F2203/45286H03F2203/45396
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Quick Facts
Patent No.
US 12,562,703
App. No.
17/937,892
Granted
Feb 24, 2026
Kind
B2
Abstract

A first correction voltage generation circuit provides a first positive or negative correction voltage for correcting an input voltage. A second correction voltage generation circuit provides a second correction voltage identical in polarity to the first correction voltage in accordance with the first correction voltage. The second correction voltage is generated to have a temperature coefficient reverse in polarity to a temperature coefficient of the first correction voltage.

Claims (19)

1 . An offset correction circuit comprising:

a current generation circuit to provide an output current having a first temperature coefficient; and

a correction voltage generation circuit to provide a correction voltage using the output current,

the correction voltage having a second temperature coefficient reverse in polarity to the first temperature coefficient.

2 . The offset correction circuit according to claim 1 , wherein

the correction voltage generation circuit includes:

a first variable resistor, connected between a first node to which the output current is provided from the current generation circuit and a second node, to generate the correction voltage when the output current passes through the first variable resistor; and

a second variable resistor, connected between the first node and a third node, to generate the correction voltage reverse in polarity to the correction voltage generated by first variable resistor when the output current passes through the second variable resistor.

3 . The offset correction circuit according to claim 2 , wherein

the first variable resistor includes

a plurality of first resistive elements connected in series and parallel between the first node and the second node, and

a plurality of first bypass switches connected in parallel to the plurality of first resistive elements, respectively,

the second variable resistor includes

a plurality of second resistive elements connected in series and parallel between the first node and the third node, and

a plurality of second bypass switches connected in parallel to the plurality of second resistive elements, respectively, and

a plurality of first bypass switch control signals to control opening and closing of the plurality of first bypass switches and a plurality of second bypass switch control signals to control opening and closing of the plurality of second bypass switches are provided to the correction voltage generation circuit.

4 . The offset correction circuit according to claim 1 , wherein

the current generation circuit is configured to provide the output current in accordance with an electrical resistance value of a bias resistive element, and

the current generation circuit includes a bias resistance variable mechanism to control a polarity of a temperature coefficient of the bias resistive element between positive and negative.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2022
From: KOJIMA, TOMOKAZU
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 061305/0259 →
Continuity (2)
Continuation 17289109
Related Publication 20230028576A1 · Jan 26, 2023
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