IP Library › Granted Patent US 12,232,260
Granted Patent B2
US 12,232,260 · App. 17/939,546 · Granted Feb 18, 2025

Electronic device having multilayered substrate and manufacturing method thereof

Inventors: Seungjin Lee (Gyeonggi-do, KR); Jonghoon Kim (Seoul, KR); Kyoungsun Kim (Gyeonggi-do, KR); Sungjoo Park (Gyeonggi-do, KR); Jinseong Yun (Gyeonggi-do, KR); Young-Ho Lee (Seoul, KR); Jeonghyeon Cho (Gyeonggi-do, KR); Heejin Cho (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H05K1/116H05K1/0298H05K3/4038H05K2201/09627
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,232,260
App. No.
17/939,546
Granted
Feb 18, 2025
Kind
B2
Abstract

An electronic device includes: a multilayered base substrate including a plurality of substrate bases stacked on each other; a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other; a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate bases of the plurality of substrate bases; and an open stub including a first end and a second end, wherein the first end is connected to a connector of the conductive line, and the second end is opened.

Claims (54)

1. An electronic device comprising:

a multilayered base substrate including a plurality of substrate bases stacked on each other;

a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other,

a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate bases of the plurality of substrate bases, wherein the conductive line is disposed between an upper surface and a lower surface of the first conductive via; and

an open stub including a first end and a second end, wherein the first end is connected to a connector of the conductive line, and the second end is opened.

2. The electronic device of claim 1 , wherein

a length of the conductive line between the first conductive via and the connector are substantially equivalent to a length of the conductive line between the second conductive via and the connector.

3. The electronic device of claim 1 , wherein

the conductive line is divided into divided conductive lines by the connector, and the divided conductive lines have substantially equivalent impedances as each other.

4. The electronic device of claim 3 , wherein

the divided conductive lines have different lengths from each other, and the divided conductive lines have different widths from each other.

5. The electronic device of claim 1 , wherein

an impedance of the open stub relates to an impedance of the conductive line.

6. The electronic device of claim 5 , wherein

an impedance of the open stub is ½ of the impedance of the conductive line.

7. The electronic device of claim 1 , wherein

the open stub is disposed on a same layer as the conductive line.

8. The electronic device of claim 1 , wherein

the open stub is a conductive via penetrating the plurality of substrate bases.

9. The electronic device of claim 1 , wherein

the open stub extends to cross the conductive line.

10. The electronic device of claim 1 , wherein

the open stub includes a first open stub and a second open stub, wherein the first open stub extends in a first direction, and the second open stub extends in a second direction different from the first direction.

11. The electronic device of claim 1 , further comprising

an additional conductive line disposed on a same layer as the conductive line and disposed adjacent to the conductive line,

wherein the open stub extends from the conductive line and is spaced apart from the additional conductive line.

12. The electronic device of claim 1 , wherein

the open stub is a plurality of open stubs, wherein the plurality of open stubs are connected to the conductive line at connectors in the conductive line, wherein the conductive line is divided into a plurality of divided conductive lines by the connectors, wherein lengths of at least two of divided conductive lines of the plurality of divided conductive lines are substantially equivalent to each other.

13. The electronic device of claim 1 , wherein

the open stub is a plurality of open stubs, and impedances of at least two open stubs of the plurality of open stubs are substantially equivalent to each other.

14. The electronic device of claim 1 , further comprising:

a first semiconductor chip attached to one side of the multilayered base substrate and electrically connected to the first conductive via; and

a second semiconductor chip attached to one side of the multilayered base substrate and electrically connected to the second conductive via.

15. The electronic device of claim 1 , further comprising:

a first semiconductor chip attached to one side of the multilayered base substrate and electrically connected to the first conductive via; and

an input/output terminal disposed on one side of the multilayered base substrate and electrically connected to the second conductive via.

16. An electronic device comprising:

a base substrate including a plurality of substrate bases stacked on each other;

at least one semiconductor chip attached to a first side of the base substrate; and

a conductive pattern connected to the at least one semiconductor chip and having a low pass filter,

wherein the low pass filter includes

a first conductive via and a second conductive via penetrating the plurality of substrate bases,

a conductive line disposed between adjacent substrate bases, of the plurality of substrate bases, that are stacked on each other, wherein the conductive line electrically connects the first conductive via and the second conductive via to each other, wherein the conductive line is disposed between an upper surface and a lower surface of the first conductive via, and

at least one open stub including a first end and a second end, wherein the first end is connected to the conductive line at a connector at which the conductive line is divided into substantially equivalent lengths, wherein the second end is opened.

17. The electronic device of claim 16 , wherein

the first conductive via includes a first via stub between a substrate base, of the plurality of substrate bases, on which the conductive line is disposed and a first side of the base substrate, and the second conductive via includes a second via stub between the substrate base on which the conductive line is disposed and a second side of the base substrate.

18. The electronic device of claim 16 , wherein

the conductive line, the at least one open stub, and the first and second via stubs form the low pass filter.

19. A method for manufacturing an electronic device, comprising:

providing a base substrate including a plurality of substrate bases, wherein a conductive line is formed on a substrate base of the plurality of substrate bases; and

forming conductive vias penetrating the base substrate and connected to respective ends of the conductive line, wherein the conductive line is disposed between an upper surface and a lower surface of the first conductive via,

wherein the conductive line is connected to an open stub of which a first end is opened in substantially a middle of the conductive line.

20. The method of claim 19 , further comprising:

before providing the base substrate, forming the conductive line and the open stub on at least one side of the substrate base.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2022
From: LEE, SEUNGJIN; KIM, JONGHOON; KIM, KYOUNGSUN; PARK, SUNGJOO; YUN, JINSEONG; LEE, YOUNG-HO; CHO, JEONGHYEON; CHO, HEEJIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 061016/0503 →
Continuity (1)
Related Publication 20230300984A1 · Sep 21, 2023
References Cited (39)
US 3662294A · Jacobs · 1972 [cited by examiner]
US 4176332A · Bachert · 1979 [cited by examiner]
US 4518931A · Rauscher · 1985 [cited by examiner]
US 4642590A · Buijs · 1987 [cited by examiner]
US 4736168A · Nagata · 1988 [cited by examiner]
US 4754229A · Kawakami · 1988 [cited by examiner]
US 5023866A · De Muro · 1991 [cited by examiner]
US 5467063A · Burns · 1995 [cited by examiner]
US 5563551A · Kashiwa · 1996 [cited by examiner]
US 6198365B1 · Yamada · 2001 [cited by examiner]
US 6388546B1 · Kikokawa · 2002 [cited by examiner]
US 6661092B2 · Shibata et al. · 2003 [cited by applicant]
US 8884644B1 · Ben Artsi · 2014 [cited by examiner]
US 9035714B2 · Mantiply · 2015 [cited by examiner]
US 9660340B2 · Yokoyama et al. · 2017 [cited by applicant]
US 9872398B1 · Doyle et al. · 2018 [cited by applicant]
US 10524351B2 · Zhang et al. · 2019 [cited by applicant]
US 11784616B2 · Chang · 2023 [cited by examiner]
US 11855650B2 · Kang · 2023 [cited by examiner]
US 20020118075A1 · Ohwada et al. · 2002 [cited by applicant]
US 20030025487A1 · Jian · 2003 [cited by examiner]
US 20040125526A1 · Nagode · 2004 [cited by examiner]
US 20070178766A1 · Banerjee · 2007 [cited by examiner]
US 20070229184A1 · Liu · 2007 [cited by examiner]
US 20120282749A1 · Gaucher et al. · 2012 [cited by applicant]
US 20140009242A1 · Mantiply · 2014 [cited by examiner]
US 20140016686A1 · Ben Artsi · 2014 [cited by examiner]
US 20150222461A1 · Motoi et al. · 2015 [cited by applicant]
US 20150311589A1 · Yokoyama et al. · 2015 [cited by applicant]
US 20160181678A1 · Robert et al. · 2016 [cited by applicant]
US 20190348974A1 · Bao · 2019 [cited by examiner]
JP 2000101303 · 2000 [cited by applicant]
JP 6362057 · 2018 [cited by applicant]
KR 1020010108226A · 2001 [cited by applicant]
KR 100873163B1 · 2008 [cited by applicant]
KR 1020130112080A · 2013 [cited by applicant]
KR 101515857B1 · 2015 [cited by applicant]
KR 101659827B1 · 2016 [cited by applicant]
Huang et al., “Stub Effect Mitigations Using Absorbing Materials”, IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, No. 8, Aug. 2016, pp. 1233-1244. [cited by applicant]