Rectifier device with minimized lateral coupling
A semiconductor device includes a semiconductor body having an upper surface, a group of first upper-level metal fingers and second upper-level metal fingers that are arranged alternatingly with one another, wherein each of the first upper-level metal fingers is electrically connected to the semiconductor body by the first lower-level conductive fingers, wherein each of the second upper-level metal fingers is electrically connected to the semiconductor body by the second lower-level conductive fingers, wherein the group of first lower-level conductive fingers and second lower-level conductive fingers defines a connection area over the upper surface, and wherein in the connection area the first upper-level metal fingers are at least partially non-overlapping with the second upper-level metal fingers.
1 . A semiconductor device, comprising:
a semiconductor body comprising an upper surface;
a group of first lower-level conductive fingers and second lower-level conductive fingers that are disposed on or above the upper surface and are arranged alternatingly with one another in a first lateral direction and; and
a group of first upper-level metal fingers and second upper-level metal fingers that are arranged alternatingly with one another in the first lateral direction,
wherein each of the first upper-level metal fingers is electrically connected to the semiconductor body by first vertical connectors that comprise one of the first lower-level conductive fingers,
wherein each of the second upper-level metal fingers is electrically connected to the semiconductor body by second vertical connectors that comprise one of the second lower-level conductive fingers,
wherein the group of first lower-level conductive fingers and second lower-level conductive fingers defines a connection area over the upper surface, and
wherein in the connection area the first upper-level metal fingers are completely non-overlapping with the second upper-level metal fingers in the first lateral direction.
2 . The semiconductor device of claim 1 , wherein in the connection area the first upper-level metal fingers are partially non-overlapping with the first lower-level conductive fingers in a second lateral direction and the second upper-level metal fingers are partially non-overlapping with the second lower-level conductive fingers in the second lateral direction, wherein the second lateral direction is orthogonal to the first lateral direction.
3 . The semiconductor device of claim 1 , wherein the semiconductor body comprises a group of p-type regions and n-type regions that are disposed within the semiconductor body and are arranged alternatingly with one another in the first lateral direction, wherein each of the first upper-level metal fingers is electrically connected to one of the p-type regions by the first vertical connectors, and wherein each of the second upper-level metal fingers is electrically connected to one of the n-type regions by the second vertical connectors.
4 . The semiconductor device of claim 3 , wherein the first lower-level conductive fingers are disposed directly on the upper surface of the semiconductor body and are each in ohmic contact with one of the p-type regions, and wherein the second lower-level conductive fingers are disposed directly on the upper surface of the semiconductor body and are each in ohmic contact with one of the n-type regions.
5 . The semiconductor device of claim 1 , further comprising an interconnection region disposed on the upper surface, wherein the interconnection region comprises one or more structured metallization layers and a dielectric region arranged between the one or more structured metallization layers and the upper surface, wherein the group of first upper-level metal fingers and second upper-level metal fingers is formed in one of the structured metallization layers.
6 . The semiconductor device of claim 5 , wherein the one or more structured metallization layers comprises a second level metallization and a third level metallization, wherein the group of first upper-level metal fingers and second upper-level metal fingers is formed in the third level metallization, and wherein the group of first lower-level conductive fingers and second lower-level conductive fingers is formed in the second level metallization.
7 . The semiconductor device of claim 5 , further comprising first and second bond pads formed in an uppermost one of the structured metallization layers, wherein the semiconductor device is configured as a rectifier device between the first and second bond pads.
8 . The semiconductor device of claim 7 , wherein the semiconductor device is configured as a bidirectional silicon-controlled rectifier device between the first and second bond pads.
9 . A semiconductor device, comprising:
a semiconductor body comprising an upper surface;
a group of first lower-level conductive fingers and second lower-level conductive fingers that are disposed on or above the upper surface and are arranged alternatingly with one another in a first lateral direction and; and
a group of first upper-level metal fingers and second upper-level metal fingers that are arranged alternatingly with one another in the first lateral direction,
wherein each of the first upper-level metal fingers is electrically connected to the semiconductor body by first vertical connectors that comprise one of the first lower-level conductive fingers,
wherein each of the second upper-level metal fingers is electrically connected to the semiconductor body by second vertical connectors that comprise one of the second lower-level conductive fingers,
wherein the group of first lower-level conductive fingers and second lower-level conductive fingers defines a connection area over the upper surface, and
wherein in the connection area the first upper-level metal fingers are at least partially non-overlapping with the second upper-level metal fingers in the first lateral direction,
wherein the first vertical connectors comprise first through-vias that are in ohmic contact with the first upper-level metal fingers, and wherein the second vertical connectors comprise second through-vias that are in ohmic contact with the second upper-level metal fingers,
wherein all of the first though-vias in the connection area are confined within a first through-via area, wherein all of the second though-vias in the connection area are confined within a second through-via area, and wherein the first through-via area is non-overlapping with the second through-via area in the first lateral direction.
10 . A semiconductor device, comprising:
a semiconductor body comprising an upper surface;
a group of first lower-level conductive fingers and second lower-level conductive fingers that are disposed on or above the upper surface and are arranged alternatingly with one another in a first lateral direction and; and
a group of first upper-level metal fingers and second upper-level metal fingers that are arranged alternatingly with one another in the first lateral direction,
wherein each of the first upper-level metal fingers is electrically connected to the semiconductor body by first vertical connectors that comprise one of the first lower-level conductive fingers,
wherein each of the second upper-level metal fingers is electrically connected to the semiconductor body by second vertical connectors that comprise one of the second lower-level conductive fingers,
wherein the group of first lower-level conductive fingers and second lower-level conductive fingers defines a connection area over the upper surface, and
wherein in the connection area the first upper-level metal fingers are at least partially non-overlapping with the second upper-level metal fingers in the first lateral direction,
wherein the semiconductor body comprises a group of p-type regions and n-type regions that are disposed within the semiconductor body and are arranged alternatingly with one another in the first lateral direction, wherein each of the first upper-level metal fingers is electrically connected to one of the p-type regions by the first vertical connectors, and wherein each of the second upper-level metal fingers is electrically connected to one of the n-type regions by the second vertical connectors,
wherein the first lower-level conductive fingers are disposed directly on the upper surface of the semiconductor body and are each in ohmic contact with one of the p-type regions, and wherein the second lower-level conductive fingers are disposed directly on the upper surface of the semiconductor body and are each in ohmic contact with one of the n-type regions.
11 . The semiconductor device of claim 10 , wherein in the connection area the first upper-level metal fingers are partially non-overlapping with the first upper-level metal fingers in the first lateral direction.
12 . The semiconductor device of claim 11 , wherein an overlap ratio of the first upper-level and second metal fingers is no more than 25%, the overlap ratio being a ratio between a combined length of the first upper-level metal fingers that overlap with the second upper-level metal fingers in the connection area and a combined length of the first upper-level metal fingers that do not overlap with the second upper-level metal fingers in the connection area.
13 . The semiconductor device of claim 12 , wherein in the connection area the overlap ratio of the first upper-level and second metal fingers is no more than 10%.