Memory channel disablement

1. An apparatus, comprising:

a plurality of memory devices comprising memory chips having memory dice; and

a memory controller coupled to the plurality of memory devices via memory channels, wherein each memory device of the plurality of memory devices is a multi-channel memory device comprising at least two memory chips located therein that are coupled to different respective first and second memory channels, and wherein the memory controller is configured to:

selectively disable one of the first memory channel or the second memory channel of a particular memory device due to a determination that a memory die within a memory chip associated with the one of the first memory channel or the second memory channel does not satisfy a reliability criterion; and

subsequent to disabling the one of the first memory channel or the second memory channel, perform a memory operation via the other of the first memory channel or the second memory channel.

2. The apparatus of claim 1 , wherein the memory controller is configured to disable the one of the first memory channel or the second memory channel prior to being coupled to the memory chip.

3. The apparatus of claim 1 , wherein the reliability criterion is associated with the presence of manufacturing defects.

4. The apparatus of claim 1 , further comprising a multiplexor, and wherein the first memory channel is a configurable channel that can be associated via the multiplexor with a first memory die of a memory chip associated with the first memory channel.

5. The apparatus of claim 1 , wherein the first memory channel and the second memory channel are included in a designated sub-group configured to be disabled.

6. The apparatus of claim 5 , wherein at least one of but not all of the memory channels in the designated sub-group are configured to be disabled.

7. The apparatus of claim 5 , wherein each memory channel in the designated sub-group is configured to be disabled.

8. The apparatus of claim 5 , wherein the designated sub-group includes a total of at least two memory channels.

9. A memory controller, comprising:

a front end portion configured to be coupled to a host via an interface to:

receive memory access requests from the host; and

provide memory access responses to the host;

a back end portion configured to be coupled to a plurality of multi-channel memory devices via a plurality of memory channels, wherein the plurality of memory channels are organized as a plurality of channel groups, and wherein each multi-channel memory device of the plurality of multi-channel memory devices comprises at least two memory chips located therein that are coupled to different respective first and second memory channels; and

memory channel circuitry configured to, prior to a memory access request being received from the host and responsive to a determination that a memory die within a memory chip of a particular one of the plurality of multi-channel memory devices has a reliability issue, disable the memory channel corresponding to the memory chip of the particular one of the plurality of multi-channel memory devices; and

wherein the memory controller is configured to, while the memory channel corresponding to the memory chip of the particular one of the plurality of multi-channel memory devices is disabled, perform a memory operation via a different memory channel corresponding to a different memory chip of the particular one of the plurality of multi-channel memory devices.

10. The memory controller of claim 9 , wherein the memory channel circuitry includes a logical gate or a multiplexor.

11. The memory controller of claim 9 , wherein the plurality of channel groups further comprise a plurality of independent respective channel groups.

12. The memory controller of claim 9 , wherein the memory channel circuitry is further configured to disable at most one memory channel in a respective channel group of the plurality of channel groups.

13. The memory controller of claim 9 , wherein each memory channel is a low-power double data rate (LPDDRx) memory channel.

14. The memory controller of claim 9 , wherein the reliability issue relates to data retention.

15. The memory controller of claim 9 , wherein the memory channel circuitry is located in a central controller portion, the back end portion, or both.

16. A system comprising:

a plurality of multi-channel memory devices; and

a memory controller comprising:

a front end portion configured to be coupled to a host via an interface to:

receive memory access requests from a host in accordance with a compute express link (CXL) protocol; and

provide memory access responses to the host in accordance with the CXL protocol;

a back end portion configured to be coupled to the plurality of multi-channel memory devices via a plurality of memory channels, wherein the plurality of memory channels are organized as a plurality of channel groups, wherein each channel group is organized into a plurality of sub-groups including at least two memory channels, and wherein the at least two memory channels of each sub-group of the plurality of sub-groups are coupled to different respective memory chips within a same one of the plurality of multi-channel memory devices; and

memory channel circuitry configured to, responsive to a determination that a memory die of particular memory chip within a particular multi-channel memory devices does not meet a reliability criterion, selectively disable the memory channel corresponding to the particular memory chip within the multi-channel memory device while maintaining remaining memory channels corresponding to the particular multi-channel memory device in an enabled state.

17. The system of claim 16 , wherein each memory channel has a same channel width.

18. The system of claim 17 , wherein each memory channel has a 8-bit width or 16-bit width.

19. The system of claim 16 , wherein each multi-channel memory device of the plurality of multi-channel memory devices includes a multi-chip package including a plurality of memory chips.