Memory die interconnections to physical layer interfaces
This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input/output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.
1 . An apparatus comprising:
at least two physical interfaces (PHYs) comprising a first PHY and a second PHY, each of the at least two PHYs comprising:
a chip select (CS) bus;
a command-and-address (CA) bus; and
at least one data input/output (DQ) bus; and
at least one memory die operably coupled to:
the first PHY via the CA bus of the first PHY and the at least one DQ bus of the first PHY; and
the second PHY via the CS bus of the second PHY.
2 . The apparatus of claim 1 , wherein the at least one memory die comprises a first memory die and the apparatus further comprises a second memory die, the second memory die operably coupled to:
the second PHY via the CA bus of the second PHY and the at least one DQ bus of the second PHY; and
the first PHY via the CS bus of the first PHY.
3 . The apparatus of claim 1 , further comprising a third memory die, the third memory die operably coupled to:
the first PHY via the CA bus of the first PHY, the at least one DQ bus of the first PHY, and the CS bus of the first PHY; or
the second PHY via the CA bus of the second PHY, the at least one DQ bus of the second PHY, and the CS bus of the second PHY.
4 . The apparatus of claim 1 , wherein the at least one memory die is not coupled to:
the first PHY via the CS bus of the first PHY; or
the second PHY via the CA bus of the second PHY and the at least one DQ bus of the second PHY.
5 . The apparatus of claim 1 , wherein:
the CS bus is configured as an L-bit bus in which ‘L’ is greater than or equal to one;
the CA bus is configured as an M-bit bus in which ‘M’ is greater than or equal to one; and
the at least one DQ bus is configured as an N-bit bus in which ‘N’ is greater than or equal to one.
6 . The apparatus of claim 1 , further comprising:
at least one memory controller (MC);
an interface operably coupled to the MC; and
wherein the first PHY and the second PHY are operably coupled to the interface.
7 . The apparatus of claim 6 , wherein the interface comprises a first interface and the apparatus further comprises:
at least one channel controller (CC);
a second interface operably coupled to the CC; and
wherein the at least one MC is operably coupled to the second interface.
8 . The apparatus of claim 1 , wherein:
the at least two PHYs comprise N PHYs in which ‘N’ is greater than or equal to two;
the at least one memory die comprise N×N memory dies; and
a first N memory dies are operably coupled to the first PHY via the CA bus and the at least one DQ bus of the first PHY;
a second N memory dies are operably coupled to the second PHY via the CA bus and the at least one DQ bus of the second PHY;
a first memory die of the first N memory dies is operably coupled to the second PHY via the CS bus of the second PHY; and
a first memory die of the second N memory dies is operably coupled to the first PHY via the CS bus of the first PHY.
9 . The apparatus of claim 8 , wherein:
the at least one DQ bus includes N DQ buses in which ‘N’ is greater than or equal to two; or
the N×N memory dies are packaged together in a stacked-die or linked-die architecture.
10 . The apparatus of claim 1 , wherein:
the at least one memory die comprises at least one memory array;
the apparatus is configured as one of a Compute Express Link™ (CXL) memory module, a single in-line memory module (SIMM), a dual in-line memory module (DIMM), or a small outline DIMM (SO-DIMM); or
the at least one memory die is one of a double data rate (DDR) die, DDR2 die, DDR3 die, DDR4 die, DDR5 die, DDR6 die, synchronous dynamic random-access memory (SDRAM) die, low-power DDR (LPDDR) SDRAM die, graphics DDR (GDDR) SDRAM die, or high-bandwidth memory (HBM) die.
11 . An apparatus comprising:
a physical interface (PHY) comprising:
at least two chip select (CS) buses comprising a first CS bus and a second CS bus;
at least two command address (CA) buses comprising a first CA bus and a second CA bus; and
at least three data input/output (DQ) buses comprising a first DQ bus, a second DQ bus, and a third DQ bus; and
at least four memory dies comprising a first memory die, a second memory die, a third memory die, and a fourth memory die,
the first memory die operably coupled to the PHY via the first CS bus, the second CA bus, and the first DQ bus;
the second memory die operably coupled to the PHY via the second CS bus, the first CA bus, and the first DQ bus;
the third memory die operably coupled to the PHY via the first CS bus, the first CA bus, and the second DQ bus; and
the fourth memory die operably coupled to the PHY via the second CS bus, the second CA bus, and the third DQ bus.
12 . The apparatus of claim 11 , wherein:
the at least three DQ buses comprise five DQ buses that include the first DQ bus, the second DQ bus, the third DQ bus, a fourth DQ bus, and a fifth DQ bus; and
the at least four memory dies comprise 20 memory dies.
13 . The apparatus of claim 12 , wherein:
a first 10 memory dies of the 20 memory dies are operably coupled to the PHY via the first CA bus; and
a second 10 memory dies of the 20 memory dies are operably coupled to the PHY via the second CA bus.
14 . The apparatus of claim 13 , wherein:
a first eight memory dies of the first 10 memory dies are operably coupled to the PHY via the first CS bus;
a remaining two memory dies of the first 10 memory dies are operably coupled to the PHY via the second CS bus;
a first eight memory dies of the second 10 memory dies are operably coupled to the PHY via the second CS bus; and
a remaining two memory dies of the second 10 memory dies are operably coupled to the at least one PHY via the first CS bus.
15 . The apparatus of claim 13 , wherein:
a first four memory dies of the first 10 memory dies are operably coupled to the at least one PHY via the first DQ bus;
a second four memory dies of the first 10 memory dies are operably coupled to the at least one PHY via the second DQ bus;
a remaining two memory dies of the first 10 memory dies are operably coupled to the at least one PHY via the fifth DQ bus;
a first four memory dies of the second 10 memory dies are operably coupled to the at least one PHY via the third DQ bus;
a second four memory dies of the second 10 memory dies are operably coupled to the at least one PHY via the fourth DQ bus; and
a remaining two memory dies of the second 10 memory dies are operably coupled to the at least one PHY via the fifth DQ bus.
16 . The apparatus of claim 11 , wherein:
the at least two CS buses are L-bit buses in which ‘L’ is greater than or equal to one;
the at least two CA buses are M-bit buses in which ‘M’ is greater than or equal to one; and
the at least three DQ buses are N-bit buses in which ‘N’ is greater than or equal to one.
17 . The apparatus of claim 11 , wherein:
the at least three DQ buses comprise four DQ buses that include the first DQ bus, the second DQ bus, the third DQ bus, and a fourth DQ bus; and
the at least four memory dies comprise five memory dies that include the first memory die, the second memory die, the third memory die, the fourth memory die, and a fifth memory die,
the fifth memory die operably coupled to the PHY via the first CS bus, the first CA bus, and the fourth DQ bus.
18 . The apparatus of claim 11 , wherein:
the at least three DQ buses comprise four DQ buses that include the first DQ bus, the second DQ bus, the third DQ bus, and a fourth DQ bus; and
the at least four memory dies comprise five memory dies that include the first memory die, the second memory die, the third memory die, the fourth memory die, and a fifth memory die,
the fifth memory die operably coupled to the PHY via the second CS bus, the second CA bus, and the fourth DQ bus.
19 . The apparatus of claim 11 , wherein:
the at least three DQ buses comprise five DQ buses that include the first DQ bus, the second DQ bus, the third DQ bus, a fourth DQ bus, and a fifth DQ bus; and
the at least four memory dies comprise six memory dies that include the first memory die, the second memory die, the third memory die, the fourth memory die, a fifth memory die, and a sixth memory die,
the fifth memory die operably coupled to the PHY via the first CS bus, the first CA bus, and the fourth DQ bus; and
the sixth memory die operably coupled to the PHY via the second CS bus, the second CA bus, and the fifth DQ bus.
20 . The apparatus of claim 11 , wherein:
the at least four memory dies comprise six memory dies that include the first memory die, the second memory die, the third memory die, the fourth memory die, a fifth memory die, and a sixth memory die,
the fifth memory die operably coupled to the PHY via the second CS bus, the first CA bus, and the first DQ bus; and
the sixth memory die operably coupled to the PHY via the first CS bus, the second CA bus, and the first DQ bus.