Method of memory time division control and related device
A method of memory time division control for a memory system comprising a plurality of memory controllers and memory devices is disclosed. The method comprises assigning a first operation timing to a first memory controller of the plurality of memory controllers and assigning a second operation timing to a second memory controller of the plurality of memory controllers, wherein the first operation timing is interleaved with the time of the second operation timing, transmitting a first chip select signal generated according to the first command signal, to a first memory device of the plurality of memory devices, and transmitting a second chip select signal generated according to the second command signal, to a second memory device of the plurality of memory devices.
1. A method of memory time division control for a memory system comprising a plurality of memory controllers and memory devices, the method comprising:
configuring a first operation timing to a first memory controller of the plurality of memory controllers and a second operation timing to a second memory controller of the plurality of memory controllers, wherein the first operation timing and the second operation timing are time interleaved, the first operation timing is used for providing a period for the first memory controller to transmit a first command signal, and the second operation timing is used for providing a period for the second memory controller to transmit a second command signal;
transmitting a first chip select signal generated according to the first command signal, to a first memory device of the plurality of memory devices; and
transmitting a second chip select signal generated according to the second command signal, to a second memory device of the plurality of memory devices.
2. The method of claim 1 , further comprising:
receiving a first data signal responsive to the first command signal, from the first memory device; and
receiving a second data signal responsive to the second command signal, from the second memory device.
3. The method of claim 2 , wherein the first command signal or the second command signal comprises a row address strobe (RAS), column address strobe (CAS) and chip select signal (CS).
4. A method of memory time division control for a memory system comprising a plurality of memory controllers, the method comprising:
receiving a first command signal transmitted by a first memory controller of the plurality of memory controllers and a second command signal transmitted by a second memory controller of the plurality of memory controllers;
determining a priority for transmitting the first command signal and the second command signal according to a predetermined priority information, wherein the predetermined priority information indicates a sequence of the plurality of memory controllers or a sequence of a plurality of commands;
generating a first chip select signal according to the first command signal with a first transmitting priority, and transmitting the first chip select signal to a first memory device of the memory system; and
generating a second chip select signal according to the second command signal with a second transmitting priority, and transmitting the second chip select signal to a second memory device of the memory system.
5. The method of claim 4 , wherein the step of determining the priority for transmitting the first command signal and the second command signal according to the predetermined priority information comprises:
determining the first command signal generated by the first memory controller has the first transmitting priority according to the sequence of the plurality of memory controllers indicated in the predetermined priority information; or
determining the first command signal has the first transmitting priority according to the sequence of a plurality of commands indicated in the predetermined priority information.
6. The method of claim 4 , further comprising:
transmitting a determination report to the first memory controller and the second memory controller, wherein the determination report indicates the transmitting priority of the first command signal and the second command signal generated by the first memory controller and the second memory controller.
7. A memory system comprising:
a plurality of memory devices, comprising a first memory device and a second memory device;
a plurality of memory controllers comprising a first memory controller and a second memory controller;
a timing management device, for configuring a first operation timing to the first memory controller and a second operation timing to the second memory controller, wherein the first operation timing and the second operation timing are time interleaved, the first operation timing is used for providing a period for the first memory controller to transmit a first command signal and the second operation timing is used for providing a period for the second memory controller to transmit a second command signal; and
a command interface device, for generating a first chip select signal and a second chip select signal according to the first command signal and the second command signal respectively, and for transmitting the first chip select signal and the second chip select signal to the first memory device and the second memory device.
8. The memory system of claim 7 , wherein the command interface device is a DDR PHY interface (DFI).
9. The memory system of claim 7 , wherein the first memory controller receives a first data signal responsive to the first command signal, from the first memory device and second memory controller receives a second data signal responsive to the second command signal, from the second memory device.