SUPER-JUNCTION DEVICE AND MANUFACTURING METHOD THEREOF
The present disclosure relates to a super-junction device and a manufacturing method thereof. In the manufacturing method, a first plurality of semiconductor pillars are formed in an epitaxial layer and a sacrificial stack is formed above the epitaxial layer. The sacrificial stack is used as a hard mask both for a body region and for a source region, and has a sidewall which controls a channel length of the super-junction device to reduce process fluctuation in different batches and improve reliability of the super-junction device.
1 . A method for manufacturing a super-junction device, comprising:
forming an epitaxial layer above a semiconductor substrate;
forming a first plurality of semiconductor pillars in the epitaxial layer;
forming a sacrificial stack above the epitaxial layer;
forming a body region in the epitaxial layer with the sacrificial stack as a first hard mask, the body region having a first edge aligned with the first hard mask;
forming a sidewall on a side surface of the sacrificial stack;
forming a source region in the body region with the sacrificial stack and the sidewall as a second hard mask, the source region having a first edge aligned with the second hard mask;
removing the sacrificial stack; and
forming a gate stack on the epitaxial layer,
wherein the gate stack extends across the first edge of the body region and the first edge of the source region such that a channel length of the super-junction device corresponds to a sidewall thickness of the sacrificial stack.
2 . The manufacturing method according to claim 1 , wherein the step of forming the first plurality of semiconductor pillars comprises:
forming a plurality of trenches in the epitaxial layer; and
epitaxially growing semiconductor layers in the plurality of trenches, respectively.
3 . The manufacturing method according to claim 1 , wherein the step of forming a first plurality of semiconductor pillars comprises: forming a plurality of doped regions in the epitaxial layer.
4 . The manufacturing method according to claim 1 , wherein a length of the first plurality of semiconductor pillars is 60% to 90% of a thickness of the epitaxial layer.
5 . The manufacturing method according to claim 4 , wherein the thickness of the epitaxial layer is 10-100 microns and the length of the first plurality of semiconductor pillars is 8-90 microns.
6 . The manufacturing method according to claim 1 , wherein the step of forming the body region comprises: forming a first photoresist on the epitaxial layer, and implanting ions through an opening between the first hard mask and the first photoresist such that the body region has a first edge aligned with the first hard mask and a second edge aligned with the first photoresist.
7 . The manufacturing method according to claim 1 , wherein the step of forming the source region comprises: forming a second photoresist on the epitaxial layer, and implanting ions through an opening between the second hard mask and the second photoresist such that the source region has a first edge aligned with the second hard mask and a second edge aligned with the second photoresist.
8 . The manufacturing method according to claim 1 , after the step of forming the gate stack, further comprising:
forming an interlayer dielectric on the epitaxial layer;
forming a conductive via through the interlayer dielectric;
forming a source electrode above the interlayer dielectric; and
forming a drain electrode above a surface of the semiconductor substrate that is opposite to the epitaxial layer,
wherein the source electrode is electrically coupled to the source region through the conductive via.
9 . The manufacturing method according to claim 8 , before forming the drain electrode, further comprising: thinning a surface of the semiconductor substrate that is opposite to the epitaxial layer.
10 . The manufacturing method according to claim 1 , wherein the body region overlaps with an upper portion of at least one of the first plurality of semiconductor pillars.
11 . The manufacturing method according to claim 1 , wherein each of the semiconductor substrate, the epitaxial layer and the source region is of a first doping type, and each of the first plurality of semiconductor pillars and the body region is of a second doping type.
12 . The manufacturing method according to claim 11 , wherein the first doping type is one of an N type and a P type, and the second doping type is the other of the N type and the P type.
13 . A super-junction device comprising:
an epitaxial layer above a semiconductor substrate;
a first plurality of semiconductor pillars in the epitaxial layer;
a body region in the epitaxial layer, at least one of the first plurality of semiconductor pillars extending below the body region;
a source region in the body region; and
a gate stack above the epitaxial layer,
wherein the gate stack extends across a first edge of the body region and a first edge of the source region such that a channel length of the super-junction device corresponds to a sidewall thickness of a sacrificial stack.
14 . The super-junction device according to claim 13 , wherein a length of the first plurality of semiconductor pillars is 60% to 90% of a thickness of the epitaxial layer.
15 . The super-junction device according to claim 14 , wherein the thickness of the epitaxial layer is 10-100 microns and the length of the first plurality of semiconductor pillars is 8-90 microns.
16 . The super-junction device according to claim 13 , further comprising:
an interlayer dielectric above the epitaxial layer;
a conductive via through the interlayer dielectric;
a source electrode above the interlayer dielectric; and
a drain electrode above a surface of the semiconductor substrate that is opposite to the epitaxial layer,
wherein the source electrode is electrically coupled to the source region through the conductive via.
17 . The super-junction device according to claim 13 , wherein the body region overlaps with an upper portion of at least one of the first plurality of semiconductor pillars.
18 . The super-junction device according to claim 13 , wherein each of the semiconductor substrate, the epitaxial layer and the source region is of a first doping type, and each of the first plurality of semiconductor pillars and the body region is of a second doping type.
19 . The super-junction device according to claim 18 , wherein the first doping type is one of an N type and a P type, and the second doping type is the other of the N type and the P type.