IP Library Granted Patent US 12,635,536
Granted Patent B2
US 12,635,536 · App. 17/948,325 · Granted May 19, 2026

Apparatuses and methods for bridge-based packaging with direct power delivery

Inventors: Gabriel H Loh (Bellevue, WA); Eric J Chapman (Austin, TX); Rahul Agarwal (Santa Clara, CA)
Assignee: Advanced Micro Devices, Inc.
H01L23/5385H01L25/0652H01L25/0655H01L25/0657H01L25/50H01L23/5384
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Quick Facts
Patent No.
US 12,635,536
App. No.
17/948,325
Granted
May 19, 2026
Kind
B2
Abstract

The disclosed computer-implemented apparatus for bridge-based packaging with direct power delivery can include an first layer stacked on a second layer. The second layer can include an interposer die and a connection die. The first layer can include a chiplet die positioned above the interposer die and a first-layer bridge die spanning across the interposer die and the connection die. The interposer die can include a set of physical interfaces and a set of routing features configured to route signals from the set of physical interfaces to the first-layer bridge die. Various other apparatuses, systems, and methods of manufacture are also disclosed.

Claims (44)

1 . An apparatus for bridge-based packaging with direct power delivery, the apparatus comprising:

a first layer parallel and adjacent to a second layer, wherein:

the second layer comprises:

an interposer die; and

a connection die;

the first layer comprises:

a first-layer bridge die spanning across the interposer die and the connection die, the first-layer bridge die being parallel to and adjacent to the interposer die; and

the interposer die comprises:

a set of routing features configured to route signals from the interposer die to the first-layer bridge die.

2 . The apparatus of claim 1 , wherein the connection die is configured to route signals from the first-layer bridge die to a fanout bridge below the connection die.

3 . The apparatus of claim 2 , wherein the connection die comprises a set of vias configured to route signals from the first-layer bridge die to the fanout bridge.

4 . The apparatus of claim 1 , wherein:

the interposer die comprises an active die; and

the first layer further comprises a chiplet die which comprises an active die.

5 . The apparatus of claim 1 , wherein the first-layer bridge die comprises a passive die.

6 . The apparatus of claim 1 , wherein the connection die comprises a passive die.

7 . The apparatus of claim 1 , wherein at least one of the first-layer bridge die and the connection die comprises an active die comprising circuitry configured to implement a built-in self-test.

8 . The apparatus of claim 1 , wherein the set of routing features comprises a set of vias.

9 . The apparatus of claim 8 , wherein the set of vias comprises, for each logical connection from a set of physical interfaces, a subset of vias connected in parallel.

10 . A system for bridge-based packaging with direct power delivery, the system comprising:

a substrate;

a mold coupled to the substrate, the mold comprising:

a fanout bridge; and

a set of electrical connectivity elements;

a multi-layer module coupled to the mold, the multi-layer module comprising:

a second layer comprising:

an interposer die; and

a connection die above a first side of the fanout bridge; and

an first layer parallel and adjacent to the second layer comprising:

a first-layer bridge die spanning across the interposer die and the connection die, the first-layer bridge die being parallel and adjacent to the interposer die;

wherein the interposer die comprises:

a set of routing features configured to route signals from the interposer die to the first-layer bridge die.

11 . The system of claim 10 , wherein a subset of the set of electrical connectivity elements are below a set of physical interfaces.

12 . The system of claim 10 , further comprising a connected module stacked on the mold and at least in part over a second side of the fanout bridge.

13 . The system of claim 10 , wherein the connection die comprises a set of vias configured to route signals from the first-layer bridge die to the fanout bridge.

14 . The system of claim 11 , wherein:

the interposer die comprises an active die; and

the first layer further comprises a chiplet die which comprises an active die.

15 . The system of claim 11 , wherein the first-layer bridge die comprises a passive die.

16 . The system of claim 11 , wherein the connection die comprises a passive die.

17 . The system of claim 11 , wherein at least one of the first-layer bridge die and the connection die comprises an active die comprising circuitry configured to implement a built-in self-test.

18 . The system of claim 11 , wherein the set of routing features comprises a set of vias.

19 . The system of claim 11 , wherein the multi-layer module comprises a chip-on-wafer module.

20 . The apparatus of claim 1 , wherein the set of routing features comprises a set of through silicon vias running through at least one layer of the interposer die and to the first-layer bridge die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2022
From: LOH, GABRIEL H; CHAPMAN, ERIC J; AGARWAL, RAHUL
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 061189/0380 →
Continuity (1)
Related Publication 20250201722A1 · Jun 19, 2025
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