Input function circuit block and output neuron circuit block coupled to a vector-by-matrix multiplication array in an artificial neural network
Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.
1. An artificial neural network comprising:
a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns;
an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and
an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.
2. The artificial neural network of claim 1 , wherein the output neuron circuit block comprises:
a charge summer comprising a plurality of sample-and-hold circuits to convert the analog currents into the output signal, the output signal comprising digital bits.
3. The artificial neural network of claim 1 , wherein the output neuron circuit block comprises:
a current summer to sum the analog currents into a single current provided as the output signal.
4. The artificial neural network of claim 1 , wherein the output neuron circuit block comprises:
a digital summer to generate the output signal, the output signal comprising digital bits.
5. The artificial neural network of claim 1 , wherein the output neuron circuit block comprises:
an integrating analog-to-digital converter to integrate the analog currents and generate the output signal, the output signal comprising digital bits.
6. The artificial neural network of claim 1 , wherein the output neuron circuit block comprises:
a successive approximation register analog-to-digital converter to convert the analog currents into the output signal, the output signal comprising digital bits.
7. The artificial neural network of claim 1 , wherein the output neuron circuit block comprises:
a sigma-delta analog-to-digital converter to convert the analog currents into the output signal, the output signal comprising digital bits.
8. A method comprising:
receiving, by an input function circuit block coupled to a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns, digital input signals;
converting, by the input function circuit block, the digital input signals into analog signals;
applying, by the input function circuit block, the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the vector-by-matrix multiplication array during a programming operation;
receiving, by an output neuron circuit block coupled to the vector-by-matrix multiplication array, analog currents from columns of the array during a read operation; and
generating, by the output neuron circuit block, an output signal in response to the analog currents.
9. The method of claim 8 , wherein the output neuron circuit block comprises:
a charge summer comprising a plurality of sample-and-hold circuits to convert the analog currents into the output signal, the output signal comprising digital bits.
10. The method of claim 8 , wherein the output neuron circuit block comprises:
a current summer to sum the analog currents into a single current provided as the output signal.
11. The method of claim 8 , wherein the output neuron circuit block comprises:
a digital summer to generate the output signal, the output signal comprising digital bits.
12. The method of claim 8 , wherein the output neuron circuit block comprises:
an integrating analog-to-digital converter to integrate the analog currents and generate the output signal, the output signal comprising digital bits.
13. The method of claim 8 , wherein the output neuron circuit block comprises:
a successive approximation register analog-to-digital converter to convert the analog currents into the output signal, the output signal comprising digital bits.
14. The method of claim 8 , wherein the output neuron circuit block comprises:
a sigma-delta analog-to-digital converter to convert the analog currents into the output signal, the output signal comprising digital bits.