3D semiconductor devices and structures with electronic circuit units
A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least eight electronic circuit units (ECUs), where each of the at least eight ECUs includes a first circuit, the first circuit including a portion of the first transistors, where each of the at least eight ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least eight ECUs includes a first vertical bus, where the first vertical bus includes greater than eight pillars and less than three hundred pillars, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.
1. A 3D device, said device comprising:
a first level comprising first transistors, said first level comprising a first interconnect;
a second level comprising second transistors, said second level overlaying said first level; and
at least eight electronic circuit units (ECUs),
wherein each of said at least eight ECUs comprises a first circuit, said first circuit comprising a portion of said first transistors,
wherein each of said at least eight ECUs comprises a second circuit, said second circuit comprising a portion of said second transistors,
wherein each of said at least eight ECUs comprises a first vertical bus,
wherein said first vertical bus comprises greater than eight pillars and less than three hundred pillars,
wherein said first vertical bus provides electrical connections between said first circuit and said second circuit,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonding regions and metal to metal bonding regions.
2. The device according to claim 1 , further comprising:
a third level comprising third transistors, said third level overlaying said second level,
wherein each of said at least eight ECUs comprises a third circuit, said third circuit comprising a portion of said third transistors.
3. The device according to claim 1 ,
wherein said second level comprises an array of memory cells.
4. The device according to claim 1 ,
wherein said second level comprises an array of DRAM cells.
5. The device according to claim 1 ,
wherein each of said at least eight ECUs comprises a second vertical bus,
wherein said second vertical bus comprises greater than eight hundred pillars.
6. The device according to claim 1 ,
wherein said first vertical bus comprises redundant vertical pillars to support increased yield for said first vertical bus.
7. The device according to claim 1 ,
wherein a plurality of said pillars are connected to one horizontal memory control line.
8. A 3D device, said device comprising:
a first level comprising first transistors, said first level comprising a first interconnect;
a second level comprising second transistors, said second level overlaying said first level; and
at least eight electronic circuit units (ECUs),
wherein each of said at least eight ECUs comprises a first circuit, said first circuit comprising a portion of said first transistors,
wherein each of said at least eight ECUs comprises a second circuit, said second circuit comprising a portion of said second transistors,
wherein each of said at least eight ECUs comprises a first vertical bus,
wherein said first vertical bus comprises greater than eight pillars and less than three hundred pillars,
wherein said first vertical bus provides electrical connections between said first circuit and said second circuit,
wherein at least one of said at least eight ECUs comprises a plurality of power delivery vertical pillars,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonding regions and metal to metal bonding regions.
9. The device according to claim 8 , further comprising:
a third level comprising third transistors, said third level overlaying said second level,
wherein each of said at least eight ECUs comprises a third circuit, said third circuit comprising a portion of said third transistors.
10. The device according to claim 8 ,
wherein said second level comprises an array of memory cells.
11. The device according to claim 8 ,
wherein said second level comprises an array of DRAM cells.
12. The device according to claim 8 ,
wherein each of said at least eight ECUs comprises a second vertical bus,
wherein said second vertical bus comprises greater than eight hundred pillars.
13. The device according to claim 8 ,
wherein said first vertical bus comprises redundant vertical pillars to support increased yield for said first vertical bus.
14. The device according to claim 8 ,
wherein a plurality of said pillars are connected to one horizontal memory control line.
15. A 3D device, said device comprising:
a first level comprising first transistors, said first level comprising a first interconnect;
a second level comprising second transistors, said second level overlaying said first level;
at least eight electronic circuit units (ECUs),
wherein each of said ECUs comprises at least one processor and at least one memory array,
wherein each of said at least eight ECUs comprises a first circuit, said first circuit comprising a portion of said first transistors,
wherein each of said at least eight ECUs comprises a second circuit, said second circuit comprising a portion of said second transistors,
wherein each of said at least eight ECUs comprises a first vertical bus,
wherein said first vertical bus comprises greater than eight pillars and less than three hundred pillars,
wherein said first vertical bus provides electrical connections between said first circuit and said second circuit,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonding regions and metal to metal bonding regions.
16. The device according to claim 15 , further comprising:
a third level comprising third transistors, said third level overlaying said second level,
wherein each of said at least eight ECUs comprises a third circuit, said third circuit comprising a portion of said third transistors.
17. The device according to claim 15 ,
wherein said second level comprises an array of memory cells.
18. The device according to claim 15 ,
wherein said second level comprises an array of DRAM cells.
19. The device according to claim 15 ,
wherein each of said at least eight ECUs comprises a second vertical bus,
wherein said second vertical bus comprises greater than eight hundred pillars.
20. The device according to claim 15 ,
wherein said first vertical bus comprises redundant vertical pillars to support increased yield for said first vertical bus.