Method for forming semiconductor device and semiconductor device

1. A method for forming a semiconductor device, comprising:

providing a stacked structure, which comprises a substrate, and sacrificial layers and semiconductor layers alternately stacked on a surface of the substrate, wherein multiple first grooves and semiconductor pillars extending in a first direction are comprised in the sacrificial layers and the semiconductor layers, and the first grooves and the semiconductor pillars are arranged at intervals;

forming word line pillars in a second direction, wherein the word line pillars intersect with the semiconductor pillars and surround the semiconductor pillars, and the first direction is perpendicular to the second direction;

forming sources and drains respectively on either side of the semiconductor pillars surrounded by the word line pillars by an epitaxial growth process;

forming bit lines on a side of the sources or the drains, wherein the bit lines are connected with the sources or the drains, the bit lines extend in a third direction, the first direction, the second direction and the third direction are pairwise perpendicular; and

forming capacitors on a side of the sources or the drains where the bit lines are not formed to form a semiconductor device.

2. The method according to claim 1 , wherein the forming the word line pillars in a second direction, wherein the word line pillars intersect with the semiconductor pillars and surround the semiconductor pillars, comprises:

removing the sacrificial layers in the semiconductor pillars to form second grooves;

forming an initial gate oxide layer and an initial dielectric layer sequentially on surfaces of the first grooves and the second grooves; and

forming the word line pillars in the second direction at preset positions of the semiconductor pillars, wherein the word line pillars intersect with and surround part of the initial dielectric layer.

3. The method according to claim 2 , further comprising: after forming the word line pillars,

removing the initial gate oxide layer and the initial dielectric layer except in the word line pillars on the surfaces of the first grooves and the second grooves to form gate oxide layers and dielectric layers in the word line pillars.

4. The method according to claim 3 , wherein a thickness of the source or the drain in the second direction is less than a sum of thicknesses of the semiconductor layer and the gate oxide layer in the second direction.

5. The method according to claim 1 , further comprising: before forming the sources or drains,

removing part of a semiconductor layer except in the word line pillars in the semiconductor pillars to form spaces;

wherein the forming the sources and the drains respectively on either side of the semiconductor pillars surrounded by the word line pillars by the epitaxial growth process comprises:

forming the sources and the drains respectively in the spaces at either side of the semiconductor pillars except in the word line pillars by the epitaxial growth process.

6. The method according to claim 5 , wherein the removing part of the semiconductor layer except in the word line pillars in the semiconductor pillars comprises:

removing a preset thickness of the semiconductor layer in the second direction from an upper surface and a lower surface of the semiconductor layer, respectively.

7. The method according to claim 2 , further comprising: after forming the sources or the drains,

forming word line isolation layers in remaining first grooves and remaining second grooves.

8. The method according to claim 1 , wherein the forming the bit lines on the side of the sources or the drains comprises:

forming a third groove extending in the third direction, wherein the third groove is located at the side of the sources or the drains, and exposes the substrate; and

forming the bit lines in the third groove.

9. The method according to claim 8 , wherein the forming the bit lines in the third groove comprises:

forming an isolation layer in the third groove;

forming multiple bit line trenches arranged at intervals in the second direction and extending in the third direction in the isolation layer; and

forming the bit lines in the bit line trenches, wherein a thickness of the bit line in the second direction is equal to a thickness of the source or the drain in the second direction.

10. The method according to claim 8 , wherein the forming the bit lines in the third groove comprises:

forming an isolation layer in the third groove;

etching back the isolation layer to form a bit line isolation layer, wherein an upper surface of the bit line isolation layer in the second direction is flush with a lower surface of the source or the drain in the second direction; and

forming the bit line with a same thickness as the source or the drain on a surface of the bit line isolation layer.

11. The method according to claim 1 , wherein the forming the capacitors on the side of the sources or the drains where the bit lines are not formed comprises:

removing sacrificial layers and part of a semiconductor layer in the stacked structure on the side of the sources or the drains where the bit lines are not formed to form first electrode layers extending in the first direction and connected to the drains;

forming sequentially a capacitive dielectric layer and a second electrode layer that cover the first electrode layer; and

filling a gap between the second electrode layers to form the capacitors.