Semiconductor memory device and method of fabricating the same
Disclosed are semiconductor memory devices and methods of fabricating the same. The method including forming a mold structure by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate, patterning the mold structure to form a first trench that exposes a first inner sidewall of the mold structure, growing a vertical semiconductor layer in the first trench such that a vertical semiconductor layer covers the first inner sidewall, using the substrate as a seed to, patterning the mold structure to form a second trench that exposes a second inner sidewall of the mold structure, forming a plurality of recesses by selectively removing the second insulating layers from the mold structure through the second trench, and horizontally growing a plurality of horizontal semiconductor layers in corresponding recesses, using the vertical semiconductor layer as a seed may be provided.
1. A method of fabricating a semiconductor memory device, the method comprising:
forming a mold structure by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate;
patterning the mold structure to form a first trench that exposes a first inner sidewall of the mold structure;
growing a vertical semiconductor layer in the first trench such that the vertical semiconductor layer covers the first inner sidewall, using the substrate as a seed;
patterning the mold structure to form a second trench that exposes a second inner sidewall of the mold structure;
forming a plurality of recesses by selectively removing the second insulating layers from the mold structure through the second trench; and
horizontally growing a plurality of horizontal semiconductor layers in corresponding recesses, using the vertical semiconductor layer as a seed,
wherein when the horizontal semiconductor layers are grown, a lattice defect occurs in at least one of the horizontal semiconductor layers, and
the lattice defect obliquely extends from a bottom surface of a corresponding one of the horizontal semiconductor layers toward a top surface of the corresponding one of the horizontal semiconductor layers.
2. The method of claim 1 , wherein the horizontal semiconductor layers are simultaneously grown from the vertical semiconductor layer.
3. The method of claim 1 , wherein the vertical semiconductor layer is grown to have a single-crystalline structure along a first crystal structure of the substrate.
4. The method of claim 3 , wherein the horizontal semiconductor layers are grown to have a single-crystalline structure along a second crystal structure of the vertical semiconductor layer.
5. The method of claim 1 , wherein forming the vertical semiconductor layer includes:
forming, in the first trench, a spacer that covers the first inner sidewall;
forming a third insulating layer that fills the first trench; and
replacing the spacer with the vertical semiconductor layer.
6. The method of claim 5 , further comprising:
after horizontally growing the horizontal semiconductor layers, selectively removing the third insulating layer; and
selectively removing the vertical semiconductor layer.
7. The method of claim 1 , further comprising:
patterning the horizontal semiconductor layers to form a plurality of semiconductor patterns that are arranged in a first direction;
forming a bit line that extends in the first direction such that the semiconductor patterns are electrically connected to the bit line; and
forming a data storage element electrically connected to each of the semiconductor patterns.
8. The method of claim 7 , further comprising:
forming a gate electrode vertically extending along the semiconductor patterns.
9. A semiconductor memory device, comprising:
a stack structure including a plurality of layers vertically stacked on a substrate, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending in a second direction from the bit line, the second direction intersecting the first direction;
a gate electrode penetrating the stack structure and vertically extending along the semiconductor pattern included in each of the plurality of layers; and
a data storage element electrically connected to the semiconductor pattern,
wherein the data storage element includes,
a first electrode electrically connected to the semiconductor pattern,
a second electrode on the first electrode, and
a dielectric layer between the first electrode and the second electrode, and
wherein the semiconductor pattern has a lattice defect that obliquely extends from a bottom surface of the semiconductor pattern toward a top surface of the semiconductor pattern.
10. The device of claim 9 , wherein the semiconductor pattern includes single-crystalline silicon.
11. The device of claim 9 , further comprising:
a first silicide pattern between the semiconductor pattern and the bit line; and
a second silicide pattern between the semiconductor pattern and the first electrode.
12. The device of claim 9 , wherein the semiconductor pattern includes:
a first impurity region electrically connected to the bit line;
a second impurity region electrically connected to the first electrode; and
a channel region between the first and second impurity regions and adjacent to the gate electrode.
13. The device of claim 9 , wherein the gate electrode includes:
a first gate electrode adjacent to a first side of the semiconductor pattern; and
a second gate electrode adjacent to a second side of the semiconductor pattern, the second side being opposite to the first side.
14. A semiconductor memory device, comprising:
a stack structure including a plurality of layers vertically stacked on a substrate, each of the plurality of layers including an insulating layer, a bit line extending in a first direction on the insulating layer, and a semiconductor pattern extending in a second direction from the bit line, the second direction intersecting the first direction;
a gate electrode penetrating the stack structure and vertically extending along the semiconductor pattern included in each of the plurality of layers; and
a data storage element electrically connected to the semiconductor pattern,
wherein the data storage element includes,
a first electrode electrically connected to the semiconductor pattern,
a second electrode on the first electrode, and
a dielectric layer between the first electrode and the second electrode,
wherein the semiconductor pattern has a lattice defect therein, and
wherein the lattice defect is at an angle of 50° to 60° with respect to a top surface of the insulating layer below the semiconductor pattern.
15. The device of claim 14 , wherein the semiconductor pattern includes single-crystalline silicon.
16. The device of claim 14 , further comprising:
a first silicide pattern between the semiconductor pattern and the bit line; and
a second silicide pattern between the semiconductor pattern and the first electrode.
17. The device of claim 14 , wherein the semiconductor pattern includes:
a first impurity region electrically connected to the bit line;
a second impurity region electrically connected to the first electrode; and
a channel region between the first and second impurity regions and adjacent to the gate electrode.
18. The device of claim 14 , wherein the gate electrode includes:
a first gate electrode adjacent to a first side of the semiconductor pattern; and
a second gate electrode adjacent to a second side of the semiconductor pattern, the second side being opposite to the first side.