Semiconductor devices
A semiconductor device includes bottom electrodes on a substrate. A supporting pattern is disposed between the bottom electrodes in a plan view. A top electrode covers the bottom electrodes and the supporting pattern. A dielectric layer is disposed between the bottom electrodes and the top electrode and between the supporting pattern and the top electrode. A capping pattern is interposed between the bottom electrodes and the dielectric layer and between the supporting pattern and the dielectric layer. The capping pattern covers at least a portion of a side surface of the supporting pattern and extends to cover a top surface of the supporting pattern and top surfaces of the bottom electrodes.
1 . A semiconductor device, comprising:
bottom electrodes on a substrate;
a supporting pattern disposed between the bottom electrodes in a plan view;
a top electrode covering the bottom electrodes and the supporting pattern;
a dielectric layer disposed between the bottom electrodes and the top electrode and between the supporting pattern and the top electrode; and
a capping pattern interposed between the bottom electrodes and the dielectric layer and between the supporting pattern and the dielectric layer,
wherein the capping pattern directly contacts at least a portion of a side surface of the supporting pattern, a top surface of the supporting pattern, and top surfaces of the bottom electrodes, and does not directly contact side surfaces of the bottom electrodes,
wherein the top surfaces of the bottom electrodes are separated from the dielectric layer by the capping pattern,
wherein the dielectric layer is in contact with the side surfaces of the bottom electrodes, and
wherein a thickness of the capping pattern is smaller than a thickness of the supporting pattern.
2 . The semiconductor device of claim 1 , wherein the capping pattern comprises a material having an etch selectivity with respect to the bottom electrodes.
3 . The semiconductor device of claim 1 , wherein the capping pattern comprises a material having an etch selectivity with respect to silicon oxide.
4 . The semiconductor device of claim 1 , wherein the capping pattern comprises at least one compound selected from silicon nitride, polysilicon, and SiCN.
5 . The semiconductor device of claim 1 , wherein a thickness of the capping pattern is in a range of about 1 nm to about 50 nm.
6 . The semiconductor device of claim 1 , wherein the bottom electrodes and the supporting pattern are vertically overlapped with the capping pattern.
7 . The semiconductor device of claim 1 , wherein each of the bottom electrodes has a pillar shape.
8 . The semiconductor device of claim 1 , wherein:
the supporting pattern comprises a plurality of supporting patterns positioned at different heights from each other; and
the capping pattern covers at least a portion of a side surface of an uppermost supporting pattern of the plurality of supporting patterns.
9 . The semiconductor device of claim 1 , wherein the top surfaces of the bottom electrodes are positioned at a height that is lower than the top surface of the supporting pattern.
10 . The semiconductor device of claim 1 , wherein the supporting pattern is in direct contact with side surfaces of the bottom electrodes.
11 . The semiconductor device of claim 1 , wherein the capping pattern is interposed between the dielectric layer and the top surface of the supporting pattern and between the dielectric layer and the top surfaces of the bottom electrodes.
12 . The semiconductor device of claim 1 , wherein the capping pattern covers an entirety of the side surface of the supporting pattern.
13 . The semiconductor device of claim 12 , wherein the top surfaces of the bottom electrodes are positioned at a height that is lower than a bottom surface of the supporting pattern.
14 . The semiconductor device of claim 12 , wherein the supporting pattern is vertically spaced apart from the bottom electrodes.
15 . A semiconductor device, comprising:
bottom electrodes on a substrate;
a supporting pattern disposed between the bottom electrodes in a plan view;
a top electrode covering the bottom electrodes and the supporting pattern;
a dielectric layer disposed between the bottom electrodes and the top electrode and between the supporting pattern and the top electrode; and
a capping pattern interposed between top surfaces of the bottom electrodes and the dielectric layer and between a top surface of the supporting pattern and the dielectric layer,
wherein the top surfaces of the bottom electrodes are positioned at a height that is lower than the top surface of the supporting pattern,
wherein the top surfaces of the bottom electrodes are separated from the dielectric layer by the capping pattern,
wherein the dielectric layer is in contact with side surfaces of the bottom electrodes,
wherein a portion of the capping pattern interposed between the top surfaces of the bottom electrodes and the dielectric layer is closer to the substrate than a portion of the capping pattern interposed between the top surface of the supporting pattern and the dielectric layer, and
wherein the capping pattern directly contacts at least a portion of a side surface of the supporting pattern, the top surface of the supporting pattern, and the top surfaces of the bottom electrodes, and does not directly contact the side surfaces of the bottom electrodes.
16 . The semiconductor device of claim 15 , wherein the top surfaces of the bottom electrodes are positioned at a height that is lower than a bottom surface of the supporting pattern.
17 . The semiconductor device of claim 15 , wherein the bottom electrodes and the supporting pattern are vertically overlapped with the capping pattern.
18 . A semiconductor device, comprising:
a substrate including an active pattern;
an impurity region arranged in the active pattern;
a word line disposed in the substrate, the word line extending to cross the active pattern;
a bit line disposed on the substrate, the bit line extending in a direction that crosses the word line;
a storage node contact disposed on the substrate, the storage node contact is electrically connected to the impurity region;
a landing pad electrically connected to the storage node contact;
a bottom electrode electrically connected to the landing pad;
an upper supporting pattern and a lower supporting pattern disposed between the bottom electrode and an adjacent bottom electrode in a plan view;
a top electrode covering the bottom electrode and the upper supporting pattern;
a dielectric layer disposed between the bottom electrode and the top electrode and between the upper supporting pattern and the top electrode; and
a capping pattern interposed between a top surface of the bottom electrode and the dielectric layer and between a top surface of the upper supporting pattern and the dielectric layer,
wherein the capping pattern directly contacts at least a portion of a side surface of the upper supporting pattern, the top surface of the upper supporting pattern, and the top surface of the bottom electrode, and does not directly contact side surfaces of the bottom electrodes,
wherein the top surfaces of the bottom electrodes are separated from the dielectric layer by the capping pattern,
wherein the dielectric layer is in contact with the side surfaces of the bottom electrodes, and
wherein a thickness of the capping pattern is smaller than a thickness of the supporting pattern.
19 . The semiconductor device of claim 18 , wherein the top surface of the bottom electrode is positioned at a height that is lower than the top surface of the upper supporting pattern.