Semiconductor device and method for fabricating the same
A capacitor includes a plurality of lower bottom electrodes, a lower supporter supporting the lower bottom electrodes and including a plurality of lower supporter openings, upper bottom electrodes formed on the lower bottom electrodes, respectively, and an upper supporter supporting the upper bottom electrodes and including a plurality of upper supporter openings, wherein the lower supporter openings and the upper supporter openings do not vertically overlap each other.
1. A method for fabricating a capacitor comprising:
forming a lower capacitor module over a semiconductor substrate, the lower capacitor module including a plurality of lower bottom electrodes and a lower supporter having a plurality of lower supporter openings that partially expose some of the lower bottom electrodes; and
forming an upper capacitor module on the lower capacitor module, the upper capacitor module including a plurality of upper bottom electrodes and an upper supporter having a plurality of upper supporter openings that partially expose some of the upper bottom electrodes,
wherein the lower supporter openings and the upper supporter openings do not vertically overlap each other.
2. The method of claim 1 , wherein the forming of the lower capacitor module includes:
stacking a first mold layer and a lower supporter layer over the semiconductor substrate;
forming a lower opening by etching the lower supporter layer and the first mold layer;
forming the lower bottom electrodes in the lower opening; and
forming the lower supporter having the lower supporter openings by etching the lower supporter layer.
3. The method of claim 1 , wherein the forming of the upper capacitor module includes:
stacking a second mold layer and an upper supporter layer over the lower bottom electrode module;
forming a top opening by etching the upper supporter layer and the second mold layer;
forming the upper bottom electrodes in the top opening; and
forming the upper supporter having the upper supporter openings by etching the upper supporter layer.
4. The method of claim 1 , wherein the lower bottom electrodes include:
fully-supported lower bottom electrodes which are fully surrounded by the lower supporter; and
partially-supported lower bottom electrodes which are partially surrounded by the lower supporter.
5. The method of claim 1 , wherein the lower supporter and the upper supporter include the same material.
6. The method of claim 1 , wherein each of the lower and upper bottom electrodes has a pillar shape.
7. The capacitor of claim 1 , wherein each of the lower bottom electrodes has a pillar shape, and each of the upper bottom electrodes has a cylinder shape.
8. The method of claim 1 , wherein each of the lower bottom electrodes has a pylinder shape, and each of the upper bottom electrodes has a pillar shape.
9. The method of claim 1 , further comprising:
a dielectric layer on the lower bottom electrodes and the upper bottom electrodes; and
a top electrode on the dielectric layer.
10. The method of claim 4 , wherein the upper bottom electrodes include:
fully-supported upper bottom electrodes which are fully surrounded by the upper supporter; and
partially-supported upper bottom electrodes which are partially surrounded by the upper supporter.
11. The method of claim 10 , wherein the fully-supported lower bottom electrodes and the partially-supported upper bottom electrodes contact each other vertically.
12. The method of claim 10 , wherein the partially-supported lower bottom electrodes and the fully-supported upper bottom electrodes are vertically contacted with each other.