Semiconductor structure and method for manufacturing same, and memory
There are provided a semiconductor structure and a method for manufacturing the same, and a memory. The method for manufacturing a semiconductor structure includes: providing a stack structure including a first dielectric layer containing a first element; forming a first groove at least penetrating through the first dielectric layer by a first etching process, wherein after the first etching process, a first etch residue is formed in the first groove; forming a first protective layer covering a side wall, at the first dielectric layer, of the first groove; and performing a first cleaning on the stack structure formed with the first protective layer to remove the first etch residue. The first groove is configured for forming a storage cell.
1 . A method for manufacturing a semiconductor structure, comprising:
providing a stack structure comprising a first dielectric layer containing a first element;
forming a pattern transfer layer on the stack structure, wherein the pattern transfer layer serves as a mask for a first etching process performed on the stack structure;
forming a first groove at least penetrating through the first dielectric layer by the first etching process, wherein after the first etching process, a first etch residue is formed in the first groove;
forming a first protective layer covering a side wall, at the first dielectric layer, of the first groove; and
performing a first cleaning on the stack structure formed with the first protective layer to remove the first etch residue;
removing the pattern transfer layer by a second etching process, after removing the first etch residue, wherein after the second etching process, a second etch residue is formed in the first groove;
forming a second protective layer covering the side wall, at the first dielectric layer, of the first groove, after the second etching process; and
performing a second cleaning on the stack structure formed with the second protective layer to remove the second etch residue;
wherein the first groove is configured for forming a storage cell.
2 . The method for manufacturing the semiconductor structure of claim 1 , wherein forming at least one of the first protective layer or the second protective layer comprises:
performing a first preprocessing on the first groove using a first cleaning agent, before performing the cleaning, so as to generate at least one of a first intermediate protective layer or a second intermediate protective layer on a surface of the first dielectric layer; and
performing a second preprocessing on the first groove formed with the at least one of the first intermediate protective layer or the second intermediate protective layer using plasma containing a second element, so that the at least one of the first intermediate protective layer or the second intermediate protective layer is changed into at least corresponding one of the first protective layer or the second protective layer.
3 . The method for manufacturing the semiconductor structure of claim 2 , wherein the first element comprises boron; the first cleaning agent comprises Caro's acid solution or deionized water whose temperature is higher than a preset temperature; and the second element comprises nitrogen.
4 . The method for manufacturing the semiconductor structure of claim 2 , wherein the first dielectric layer comprises a first dielectric sublayer for forming a bottom support layer and a second dielectric sublayer located on the first dielectric sublayer; correspondingly, the first protective layer comprises a first protective sublayer and a second protective sublayer, and the second protective layer comprises a third protective sublayer and a fourth protective sublayer;
forming the at least one of the first protective layer or the second protective layer comprises:
forming at least one of the first protective sublayer or the third protective sublayer covering the first dielectric sublayer in the side wall of the first groove, and forming at least one of the second protective sublayer or the fourth protective sublayer covering the second dielectric sublayer in the side wall of the first groove.
5 . The method for manufacturing the semiconductor structure of claim 4 , wherein materials for forming the first dielectric sublayer comprise silicon boron nitrogen, materials for forming the second dielectric sublayer comprise boron-phosphorosilicate glass, materials for forming at least one of the first protective sublayer or the third protective sublayer comprise silicon nitride, and materials for forming at least one of the second protective sublayer or the fourth protective sublayer comprise silicon oxynitride.
6 . The method for manufacturing the semiconductor structure of claim 1 , wherein the stack structure further comprises: a second dielectric layer between the first dielectric layer and the pattern transfer layer; the first groove also penetrates through the second dielectric layer; and the second dielectric layer is configured for forming a middle support layer and a top support layer; the method further comprises:
forming in the first groove a first conductive layer covering a side wall and a bottom of the first groove, after removing the second etch residue;
removing a part of the first dielectric layer and a part of the second dielectric layer;
forming a dielectric medium layer covering the first conductive layer; and
forming a second conductive layer covering the dielectric medium layer.
7 . The method for manufacturing the semiconductor structure of claim 1 , wherein materials for forming the pattern transfer layer comprise polysilicon.