FERROELECTRIC TUNNEL JUNCTION DEVICES FOR LOW VOLTAGE AND LOW TEMPERATURE OPERATION
An integrated circuit (IC) die includes a plurality of ferroelectric tunnel junction (FTJ) devices, where at least one FTJ of the plurality of FTJ devices comprises first electrode, a second electrode, ferroelectric material disposed between the first and second electrodes, and interface material disposed between at least one of the first and second electrodes and the ferroelectric material. Other embodiments are disclosed and claimed.
1 . An integrated circuit (IC) die, comprising a plurality of ferroelectric tunnel junction (FTJ) devices, wherein at least one FTJ of the plurality of FTJ devices comprises:
first electrode;
a second electrode;
ferroelectric material disposed between the first and second electrodes; and
interface material disposed between at least one of the first and second electrodes and the ferroelectric material.
2 . The IC die of claim 1 , wherein the interface material is formed in a vertical orientation that spans two or more layers of the IC die.
3 . The IC die of claim 1 , wherein the interface material is formed in a horizontal orientation on a single layer of the IC die.
4 . The IC die of claim 1 , further comprising a memory circuit that includes the at least one FTJ device.
5 . The IC die of claim 1 , further comprising a diode that includes the at least one FTJ device.
6 . The IC die of claim 1 , further comprising:
block material disposed between at least one of the first and second electrodes and the ferroelectric material.
7 . The IC die of claim 6 , further comprising a metal-insulator-metal (MIM) capacitor that includes the at least one FTJ device.
8 . A system, comprising:
a substrate;
a power supply; and
an integrated circuit (IC) die attached to the substrate and coupled to the power supply, the IC die comprising a plurality of ferroelectric tunnel junction (FTJ) devices, wherein at least one FTJ of the plurality of FTJ devices comprises:
a first electrode;
a second electrode;
ferroelectric material disposed between the first and second electrodes; and
interface material disposed between at least one of the first and second electrodes and the ferroelectric material.
9 . The system of claim 8 , further comprising one or more of a diode and a memory circuit that includes the at least one FTJ device.
10 . The system of claim 8 , wherein the at least one FTJ device further comprises:
block material disposed between at least one of the first and second electrodes and the ferroelectric material.
11 . The system of claim 10 , further comprising a metal-insulator-metal (MIM) capacitor that includes the at least one FTJ device.
12 . The system of claim 8 , further comprising:
a cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below −25° C.
13 . The system of claim 12 , wherein the IC die comprises a plurality of metallization layers over a front side of the plurality of FTJ devices, the metallization layers to provide signal routing for the plurality of FTJ devices, and wherein the cooling structure is over the plurality of metallization layers.
14 . The system of claim 13 , wherein the cooling structure comprises a plurality of microchannels in the IC die and over the plurality of metallization layers, the microchannels to convey a heat transfer fluid therein.
15 . The system of claim 14 , wherein the cooling structure further comprises a chiller mounted to the IC die over the microchannels, the chiller comprising one of a solid body comprising second microchannels to convey a second heat transfer fluid therein or a heat sink for immersion in a low-boiling point liquid.
16 . The system of claim 12 , wherein the cooling structure is to convey liquid nitrogen to achieve an operating temperature at or below about −196° C.
17 . A method, comprising:
receiving a substrate;
forming a first metallization layer over the substrate that includes a first electrode of a ferroelectric tunnel junction (FTJ) device;
forming a first dielectric layer over the first metallization layer, wherein the first dielectric layer includes a ferroelectric material of the FTJ device on the first electrode;
forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer includes an interface material of the FTJ device on the ferroelectric material; and
forming a second metallization layer over the second dielectric layer, wherein the second metallization layer includes a second electrode of the FTJ device on the interface material.
18 . The method of claim 17 , further comprising:
forming a memory circuit that includes the FTJ device.
19 . The method of claim 17 , further comprising:
forming a diode that includes the FTJ device.
20 . The method of claim 17 , further comprising:
forming a third dielectric layer over one of the first metallization layer, the first dielectric layer, and the second dielectric layer, wherein the third dielectric layer includes a blocking material of the FTJ device.
21 . The method of claim 20 , further comprising:
forming a metal-insulator-metal (MIM) capacitor that includes the FTJ device.
22 . The method of claim 17 , further comprising:
forming a cooling structure over the first and second metallization layers, wherein the cooling structure is operable to remove heat from the FTJ device to achieve an operating temperature at or below −25° C.