Semiconductor device with peripheral gate structure and method for fabricating the same
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area; and a peripheral gate structure including: a peripheral gate dielectric layer inwardly positioned in the peripheral area of the substrate and including a U-shaped cross-sectional profile; a peripheral gate conductor including a bottom portion positioned on the peripheral gate dielectric layer and a neck portion positioned on the bottom portion; and a peripheral gate capping layer positioned on the peripheral gate dielectric layer and the bottom portion, and surrounding the neck portion. A top surface of the peripheral gate capping layer and a top surface of the neck portion are substantially coplanar.
1. A semiconductor device, comprising:
a substrate comprising an array area and a peripheral area;
a peripheral gate structure comprising:
a peripheral gate dielectric layer inwardly positioned in the peripheral area of the substrate and comprising a U-shaped cross-sectional profile;
a peripheral gate conductor comprising a bottom portion positioned on the peripheral gate dielectric layer and a neck portion positioned on the bottom portion; and
a peripheral gate capping layer positioned on the peripheral gate dielectric layer and the bottom portion, and surrounding the neck portion; and
an array gate structure positioned in the array area of the substrate;
wherein a top surface of the peripheral gate capping layer and a top surface of the neck portion are substantially coplanar;
wherein a width of the peripheral gate structure is greater than a width of the array gate structure;
wherein the array gate structure comprising:
an array gate dielectric layer inwardly positioned in the array area of the substrate;
an array gate conductor positioned on the array gate dielectric layer; and
an array gate capping layer positioned on the array gate conductor;
wherein the peripheral gate dielectric layer and the array gate dielectric layer comprise different materials;
wherein the peripheral gate conductor and the array gate conductor comprise different materials.
2. The semiconductor device of claim 1 , wherein the peripheral gate capping layer and the array gate capping layer comprise the same material; wherein the peripheral gate structure comprises a top portion positioned on the neck portion.
3. The semiconductor device of claim 2 , further comprising a peripheral impurity region positioned in the peripheral area of the substrate and adjacent to the peripheral gate capping layer; wherein a bottom surface of the peripheral impurity region is at a vertical level lower than a bottom surface of the peripheral gate capping layer.
4. The semiconductor device of claim 3 , wherein a width of the top portion is greater than a width of the neck portion.
5. The semiconductor device of claim 3 , wherein a width of the top portion and a width of the neck portion are substantially the same.
6. The semiconductor device of claim 3 , wherein a bottom surface of the peripheral gate structure is at a vertical level lower than a bottom surface of the array gate structure.