Selective ferroelectric deployment for single-transistor, multiple-capacitor devices
A memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. The shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. The memory device may include an integrated circuit die and be coupled to a power supply. Forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.
1 . A memory device, comprising:
a plurality of vertically aligned ferroelectric capacitors, wherein individual ones of the ferroelectric capacitors comprise:
an outer plate;
a ferroelectric layer internal to the outer plate, wherein individual ones of the ferroelectric layers are not contiguous to each other; and
an individual portion of a shared inner plate extending through individual ones of the ferroelectric layers and the outer plates, wherein the inner plate has a first width within a first one of the ferroelectric capacitors, a second width within a second one of the ferroelectric capacitors, and a third width between the first and second ones of the ferroelectric capacitors, the third width being greater than the first and second widths; and
an access transistor coupled to the inner plate.
2 . The memory device of claim 1 , wherein a portion of the inner plate at the third width is vertically between the ferroelectric layers of the first one of the ferroelectric capacitors and the second one of the ferroelectric capacitors.
3 . The memory device of claim 2 , further comprising an insulator between vertically adjacent outer plates, wherein the insulator comprises oxygen and carbon, or predominantly silicon and oxygen, and wherein the portion of the inner plate at the third width is on the insulator between the first one of the ferroelectric capacitors and the second one of the ferroelectric capacitors.
4 . The memory device of claim 3 , wherein the insulator further comprises an organic material, and the portion of the inner plate at the third width is on the organic material.
5 . The memory device of claim 1 , wherein individual ones of the ferroelectric layers comprise a scallop shape.
6 . The memory device of claim 1 , wherein individual ones of the ferroelectric layers comprise a non-perovskite metal oxide in an orthorhombic or tetragonal phase.
7 . The memory device of claim 6 , wherein individual ones of the ferroelectric layers comprise hafnium and oxygen.
8 . The memory device of claim 7 , wherein individual ones of the ferroelectric layers comprise predominantly hafnium, zirconium, and oxygen.
9 . The memory device of claim 1 , wherein the individual ones of the outer plates comprises predominantly tungsten, molybdenum, or both titanium and nitrogen.
10 . The memory device of claim 1 , further comprising:
an integrated circuit (IC) die coupled to a power supply, the IC die comprising the plurality of vertically aligned ferroelectric capacitors and the access transistor.
11 . A memory device, comprising:
a plurality of vertically aligned ferroelectric capacitors, each of the ferroelectric capacitors comprising:
a ferroelectric layer within an outer plate, wherein each of the ferroelectric layers are not contiguous to each other; and
a portion of a shared inner plate extending through the ferroelectric layers and the outer plates, wherein the inner plate has a first width extending between a first of the ferroelectric layers within a first of the ferroelectric capacitors, a second width extending between a second of the ferroelectric layers within a second of the ferroelectric capacitors, and a third width extending between an insulator layer between the first of the ferroelectric capacitors and the second of the ferroelectric capacitors, the third width being greater than the first and second widths; and
a transistor coupled to the inner plate.
12 . The memory device of claim 11 , wherein a portion of the inner plate at the third width is vertically between the ferroelectric layers of the first of the ferroelectric capacitors and the second of the ferroelectric capacitors.
13 . The memory device of claim 12 , further comprising an insulator between vertically adjacent outer plates, wherein the insulator comprises oxygen and carbon, or predominantly silicon and oxygen, and wherein the portion of the inner plate at the third width is on the insulator between the first of the ferroelectric capacitors and the second of the ferroelectric capacitors.
14 . The memory device of claim 13 , wherein the insulator further comprises an organic material, and the portion of the inner plate at the third width is on the organic material.
15 . The memory device of claim 11 , wherein the ferroelectric layers comprise a scallop shape.
16 . The memory device of claim 11 , wherein the ferroelectric layers comprise a non-perovskite metal oxide in an orthorhombic or tetragonal phase.
17 . The memory device of claim 16 , wherein the ferroelectric layers comprise hafnium and oxygen.
18 . The memory device of claim 11 , wherein the ferroelectric layers comprise predominantly hafnium, zirconium, and oxygen.
19 . The memory device of claim 11 , wherein the outer plates comprises predominantly tungsten, molybdenum, or both titanium and nitrogen.
20 . The memory device of claim 11 , further comprising:
an integrated circuit (IC) die coupled to a power supply, the IC die comprising the plurality of vertically aligned ferroelectric capacitors and the transistor.